參數(shù)資料
型號: SLB128B
廠商: National Semiconductor Corporation
英文描述: Transmitter with built-in scaler for LVDS Display Interface (LDI)
中文描述: 發(fā)射器內(nèi)置的LVDS顯示接口(低密度脂蛋白縮放)
文件頁數(shù): 19/48頁
文件大小: 650K
代理商: SLB128B
Host Control Register Descriptions
(Continued)
Register Name: CFG1
Address Offset: 08h
Default Value:
Access Method: R/W
39h
Bit
0
1
2
Description
Soft Power Down; 0 = Power Down, 1 = Normal Operation
Reserved
BPASS (1 = bypass, 0 = non-bypass)
This field is valid only when DUAL pin is 0V or
1
2
V
CC
. Note: When image scaling is not required power savings
can be achieved in bypass mode.
DSEL
0= Input clock is differential (recommended for clocks above 65 MHz),
1= input clock is single-ended
HEN (HSYNC enable)
0= HSYNC is transmitted as a fixed low,
1= HSYNC is same as input
VEN (VSYNC enable)
0= VSYNC is transmitted as a fixed low,
1= VSYNC is same as input
Reserved
3
4
5
7:6
D
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