參數(shù)資料
型號: SLA 24C32
廠商: SIEMENS AG
元件分類: DRAM
英文描述: 32 Kbit (4096 ×8 bit) Serial CMOS-EEPROM with IIC Synchronous 2-Wire Bus(32K位(4096 ×8 位)串行CMOS-EEPROM(帶有IIC同步2線控制))
中文描述: 32千位(4096 × 8位)串行的CMOS EEPROM,帶有國際進(jìn)口同步2線巴士(32K的位(4096 × 8位)串行的CMOS EEPROM的(帶有國際進(jìn)口同步2線控制))
文件頁數(shù): 18/28頁
文件大小: 368K
代理商: SLA 24C32
SLx 24C32
Semiconductor Group
18
1999-02-02
6.2
The EEPROM content is read without setting an EEPROM address, in this case the
current content of the address counter will be used (e.g. to continue a previous read
operation after the Master has served an interrupt).
Current Address Read
Figure 12
Current Address Read
Transmission of CSR
For a current address read the master generates a START
condition, which is followed by the command byte CSR (Chip
Select Read). The receipt of the CSR-byte is acknowledged
by the EEPROM with a low on the SDA line.
During the next eight clock pulses the EEPROM transmits the
data byte and increments the internal address counter by one
byte.
During the following clock cycle the masters releases the bus
and then transmits the STOP condition.
Transmission of
EEPROM Data
STOP Condition from
Master
Command Byte
CSR
S
P
A
C
K
S
T
A
R
T
T
O
P
S
Bus Activity
Master
SDA Line
Bus Activity
EEPROM
IED02132
Data Byte
1
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