參數(shù)資料
型號(hào)： SL28506BZIT
廠(chǎng)商： SILICON LABORATORIES
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64
封裝： 6 X 17 MM, HALOGEN FREE AND ROHS COMPLIANT, MO-153EF, TSSOP-64
文件頁(yè)數(shù)： 22/28頁(yè)
文件大?。?/td> 261K
代理商： SL28506BZIT
SL28506
.........................DOC #: SP-AP-0021 (Rev AA) Page 3 of 28
26
VDD_SRC_IO
PWR
IO power supply for SRC outputs.
27
SRC4
O, DIF 100MHz Differential serial reference clocks.
28
SRC4#
O, DIF 100MHz Differential serial reference clocks.
29
VSS_SRC
GND
Ground for outputs.
30
SRC9
O, DIF 100MHz Differential serial reference clocks.
31
SRC9#
O, DIF 100MHz Differential serial reference clocks.
32
SRC11#/OE#_9
I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#9 Input controlling SRC9
(Default SRC11, 100MHz clock)
33
SRC11/OE#_10
I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#10 Input controlling SRC10.
(Default SRC11, 100MHz clock)
34
SRC10
O, DIF 100MHz Differential serial reference clocks.
35
SRC10#
O, DIF 100MHz Differential serial reference clocks.
36
VDD_SRC_IO
PWR
IO Power supply for SRC outputs.
37
SRC5#CPU_STP#
I/O,
Dif
3.3V tolerant input for stopping CPU outputs/100MHz Differential serial reference
clocks.
38
SRC5/PCI_STP#
I/O,
Dif
3.3V tolerant input for stopping PCI and SRC outputs/100MHz Differential serial
reference clocks.
39
VDD_SRC
PWR
3.3V Power supply for SRC PLL.
40
SRC6#
O, DIF 100MHz Differential serial reference clocks.
41
SRC6
O, DIF 100MHz Differential serial reference clocks.
42
VSS_SRC
GND
Ground for outputs.
43
SRC7#/OE#_6
I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#6 Input controlling SRC6.
(Default SRC7, 100MHz clock).
44
SRC7/OE#_8
I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8.
(Default SRC7, 100MHz clock).
45
VDD_SRC_IO
PWR
0.7V power supply for SRC outputs.
46
SRC8#/CPU2#_ITP#
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD
assertion = SRC8
ITP_EN = 1 @ CKPWRGD assertion = CPU2
(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2)
47
SRC8/CPU2_ITP
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD
assertion = SRC8
ITP_EN = 1 @ CKPWRGD assertion = CPU2
(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2)
48
IO_VOUT
PWR
Integrated Linear Regulator Control.
49
VDD_CPU_IO
PWR
IO Power supply for CPU outputs.
50
CPU1#
O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2)
51
CPU1
O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2)
52
VSS_CPU
GND
Ground for outputs.
53
CPU#0
O, DIF Differential CPU clock outputs.
54
CPU0
O, DIF Differential CPU clock outputs.
55
VDD_CPU
PWR
3.3V Power supply for CPU PLL.
56
CKPWRGD/PD#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, FS_D, SRC5_SEL, and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
64 TSSOP Pin Definition (continued)
Pin No.
Name
Type
Description
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