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參數(shù)資料
| 型號： | SL2309ZI-1T |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 2309 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 4.40 MM, ROHS COMPLIANT, TSSOP-16 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 157K |
| 代理商： | SL2309ZI-1T |
Rev 1.3, July 31, 2007
Page 2 of 12
SL2309
Pin Configuration
CLKA1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
CLKIN
CLKA2
VDD
GND
CLKB1
CLKB2
S2
Pin Description
16-Pin SOIC and TSSOP
Pin
Number
Pin Name
Pin Type
Pin Description
1
CLKIN
Input
Reference Frequency Clock Input. Weak pull-down (250k
Ω).
2
CLKA1
Output
Buffered Clock Output, Bank A. Weak pull-down (2
50kΩ).
3
CLKA2
Output
Buffered Clock Output, Bank A. Weak pull-down (2
50kΩ).
4
VDD
Power
3.3V Power Supply.
5
GND
Power
Power Ground.
6
CLKB1
Output
Buffered Clock Output, Bank B. Weak pull-down (2
50kΩ).
7
CLKB2
Output
Buffered Clock Output, Bank B. Weak pull-down (2
50kΩ).
8
S2
Input
Select Input, select pin S2. Weak pull-up (2
50kΩ).
9
S1
Input
Select Input, select pin S1. Weak pull-up (2
50kΩ).
10
CLKB3
Output
Buffered Clock Output, Bank B. Weak pull-down (2
50kΩ).
11
CLKB4
Output
Buffered Clock Output, Bank B. Weak pull-down (2
50kΩ).
12
GND
Power
Power Ground.
13
VDD
Power
3.3V Power Supply.
14
CLKA3
Output
Buffered Clock Output, Bank A. Weak pull-down (2
50kΩ).
15
CLKA4
Output
Buffered Clock Output, Bank A. Weak pull-down (2
50kΩ).
16
CLKOUT
Output
Buffered Clock Output, PLL Internal Feedback Output. Weak pull-down (2
50kΩ).
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