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參數(shù)資料
| 型號： | SL2309ZI-1T |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 2309 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 4.40 MM, ROHS COMPLIANT, TSSOP-16 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 157K |
| 代理商： | SL2309ZI-1T |
Rev 1.3, July 31, 2007
Page 7 of 12
SL2309
Switching Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades
Notes:
1. For the given maximum loading conditions. See CL in Operating Conditions Table.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Symbol
Description
Condition
Min
Typ
Max
Unit
FMAX1
Maximum Frequency
(Input=Output )
[1]
All Active PLL Modes
High drive (-1H). All outputs CL=15pF
10
–
140
MHz
High drive (-1H), All outputs CL=30pF
10
–
100
MHz
Standard drive, (-1), All outputs CL=15pf
10
–
100
MHz
Standard drive, (-1), All outputs CL=30pf
10
–
66
MHz
FMAX2
Maximum Frequency
(Input=Output )
[1]
PLL Bypass Mode
(S2=1 and S1=0)
High drive (-1H). All outputs CL=15pF
0
–
140
MHz
High drive (-1H), All outputs CL=30pF
0
–
100
MHz
Standard drive, (-1), All outputs CL=15pf
0
–
100
MHz
Standard drive, (-1), All outputs CL=30pf
0
–
66
MHz
INDC
Input Duty Cycle
Measured at 1.4V, Fout=66MHz, CL=15pF
30
50
70
%
OUTDC1
Output Duty Cycle
Measured at 1.4V, Fout=66MHz, CL=15pF
[2]
40
50
60
%
OUTDC2
Output Duty Cycle
Measured at 1.4V, Fout=66MHz, CL=15pF
[2]
40
50
60
%
tr/f
Rise, Fall Time (3.3V)
(Measured at: 0.8 to 2.0V)
[2]
High drive (-1H), CL=15pF
–
1.5
ns
High drive (-1H), CL=30pF
–
1.8
ns
Standard drive (-1), CL=15pF
–
2.2
ns
Standard drive (-1), CL=30pF
–
2.5
ns
t1
Output-to-Output Skew
(Measured at VDD/2)
[2]
All outputs CL=0 or equally loaded, -1 or
-1H drives
–
70
150
ps
t2
Product-to-Product Skew
(Measured at VDD/2)
[2]
All outputs CL=0 or equally loaded, -1 or
-1H drives
–
180
400
ps
t3
Delay Time, CLKIN Rising
Edge to CLKOUT Rising
Edge
(Measured at VDD/2)
[2]
PLL Bypass mode
Only when S2=1 and S1=0
1.5
5
8.7
ns
PLL enabled
All active PLL modes
–220
–
220
ps
tPLOCK
PLL Lock Time
Time from 90% of VDD to valid clocks on
all the output clocks
[2]
–
1.0
ms
CCJ
Cycle-to-cycle Jitter
Fin=Fout=66 MHz, <CL=15pF, -1H drive
[2]
–
70
140
ps
Fin=Fout=66 MHz, <CL=15pF, -1 drive
–
75
150
ps
Fin=Fout=66 MHz, <CL=30pF, -1H drive
–
80
160
ps
Fin=Fout=66 MHz, <CL=30pF, -1 drive
–
85
170
ps
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