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參數(shù)資料
| 型號(hào)： | SL15102DI-XXX |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, DSO8 |
| 封裝： | 3 X 3 MM, 0.75 MM HEIGHT, ROHS COMPLIANT, TDFN-8 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 308K |
| 代理商： | SL15102DI-XXX |
Rev 1.0, October 3, 2008
Page 2 of 12
SL15102
Pin Configuration
8-Pin TDFN
Pin Description
Pin
Number
Pin Name
Pin Type
Pin Description
1
SSCLK2
REFCLK2
Output
SSCLK2 or REFOUT2 clock output. The frequency at this pin is
synthesized by internal PLL with our without spread or buffered output of
input crystal or clock.
2
SSCLK3
REFCLK3
MF2
Output
SSCLK3 or REFOUT3 clock output. The frequency at this pin is
synthesized by internal PLL with our without spread or buffered output of
input crystal or clock. This pin can be also programmed as MF using one
of the control functions of PD#, OE, SSON# or FS (frequency or spread
% select).
3
VDD
Power
Positive power supply. 3.3V to 2.5V +/-10%.
4
VDD
Power
Positive power supply. 3.3V to 2.5V +/-10%.
5
XOUT
Output
Crystal output. Leave this pin unconnected (floating) if an external clock
input is used.
6
XIN/CLKIN
Input
External crystal or clock input.
7
SSCLK1
REFCLK1
MF1
Output
SSCLK1 or REFOUT1 clock output. The frequency at this pin is
synthesized by internal PLL with our without spread or buffered output of
input crystal or clock. This pin can be also programmed as MF using one
of the control functions of PD#, OE, SSON# or FS (frequency or spread
% select).
8
VSS
Power
Power supply ground.
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