參數(shù)資料
型號: SL15100ZIT-XXX
廠商: SILICON LABORATORIES
元件分類: 時鐘產(chǎn)生/分配
英文描述: 200 MHz, OTHER CLOCK GENERATOR, PDSO8
封裝: 0.173 INCH, ROHS COMPLIANT, TSSOP-8
文件頁數(shù): 2/16頁
文件大小: 379K
代理商: SL15100ZIT-XXX
Rev 1.8, August 10, 2007
Page 10 of 16
SL15100
(SSCLK – Pin 7)
REFCLK=Off
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ4
CLKIN=SSCLK=166MHz, 2%Spread
REFCLK=On
-
110
145
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ5
CLKIN=SSCLK=66MHz, 2%Spread
REFCLK=On
-
115
155
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ6
CLKIN=SSCLK=33MHz, 2%Spread
REFCLK=On
-
190
255
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 6)
CCJ7
CLKIN=SSCLK=166MHz, 2%Spread
REFCLK=On
-
90
115
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 6)
CCJ8
CLKIN=SSCLK=66MHz, 2%Spread
REFCLK=On
-
110
145
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 6)
CCJ9
CLKIN=SSCLK=33MHz, 2%Spread
REFCLK=On
-
145
195
ps
Power-down Time
tPD
Time from PD# falling edge to Hi-Z at
outputs (Asynchronous)
-
150
350
ns
Power-up Time
(Crystal or Resonator)
tPU1
Time from PD# rising edge to valid
frequency at outputs (Asynchronous)
-
3.5
5.0
ms
Power-up Time
(Clock)
tPU2
Time from PD# rising edge to valid
frequency at outputs (Asynchronous)
-
2.0
3.0
ms
Output Enable Time
tOE
Time from OE falling edge to Hi-Z at
outputs (Asynchronous)
-
150
350
ns
Output Disable Time
tOD
Time from OE falling edge to Hi-Z at
outputs (Asynchronous)
-
150
350
ns
Spread Percent Range
SPR
SSCLK-1/2
0.25
-
5.0
%
Spread Percent Variation
ΔSS%
Variation of programmed Spread %
-20
-
20
%
Modulation Frequency
FMOD
Programmable, 31.5 kHz standard
30
31.5
120
kHz
DC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C
Description
Symbol
Condition
Min
Typ
Max
Unit
Operating Voltage
VDD
VDD+/-10%
2.25
2.5
2.75
V
Input Low Voltage
VIL
CMOS Level, Pins 4 and 8
0
-
0.3VDD
V
Input High Voltage
VIH
CMOS Level, Pins 4 and 8
0.7VDD
-
VDD
V
Output High Voltage
VOH1
IOH=6mA , Pins 6 and 7
VDD-0.4
-
V
Output Low Voltage
VOL1
IOL=6mA, Pins 6 and 7
-
0.4
V
Input High Current
IIH
VIN=VDD, Pins 4 and 8
If no pull-up/down resister used
-
15
μA
Input Low Current
IIL
VIN=GND, Pins 4 and 8
If no pull-up/down resister used
-
15
μA
Pull-up or Down Resistors
RPU/D
Vin=VDD or GND
90
160
230
k
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