參數(shù)資料
型號(hào): SK12439PJ
元件分類(lèi): 時(shí)鐘產(chǎn)生/分配
英文描述: 800 MHz, OTHER CLOCK GENERATOR, PQCC28
封裝: PLASTIC, LCC-28
文件頁(yè)數(shù): 16/18頁(yè)
文件大小: 233K
代理商: SK12439PJ
7
Revision 1/February 9, 2001
www.semtech.com
HIGH-PER.ORMANCE PRODUCTS
SK12439
ADVANCED
Application Information (continued)
PLL 12439
M COUNTER
SHIFT
REG
12-BIT
0
1
N DIVIDE
(1, 2, 4, 8)
LATCH
Reset
FREF
S_CLOCK
S_DATA
S_LOAD
P_LOADB
MCNT
VC0
Shift Register Out
DECODE
FDIV4
MCNT/2
LOW
FOUT
MCNT/2
FREF
HIGH
7
0
SEL_CLK
T0
T1
T2
TEST
MUX
FOUT
(VIA ENABLE GATE)
TEST
T2 = T1 = 1, T0 = 0: Test Mode (PLL Bypass)
S_CLOCK is selected, MCNT is on TEST output, S_CLOCK divide by N is on FOUT pin
P_LOADB acts as reset for test pin latch. When latch reset, T2 data is shifted out of TEST pin.
Figure 4. Serial Test Clock Block Diagram
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