參數(shù)資料
型號: SIP21102DR-30-E3
廠商: VISHAY SILICONIX
元件分類: 固定正電壓單路輸出LDO穩(wěn)壓器
英文描述: 3 V FIXED POSITIVE LDO REGULATOR, 0.22 V DROPOUT, PDSO5
封裝: ROHS COMPLIANT, SC-70, 5 PIN
文件頁數(shù): 10/10頁
文件大?。?/td> 141K
代理商: SIP21102DR-30-E3
Document Number: 73213
S09-1453-Rev. E, 03-Aug-09
www.vishay.com
9
Vishay Siliconix
SiP21102
DETAILED DESCRIPTION
The SiP21102 is a low-noise, low drop-out and low quiescent
current linear voltage regulator, packaged in a small footprint
SC70-5 package. The SiP21102 can supply loads up to
150 mA. As shown in the block diagram, the circuit consists
of a bandgap reference error, amplifier, P-Channel pass
transistor and feedback resistor string. Additional blocks, not
shown in the block diagram, include a precise current limiter,
reverse battery and current protection and thermal sensor.
Thermal Overload Protection
The thermal overload protection limits the total power
dissipation and protects the device from being damaged.
When the junction temperature exceeds 150 °C, the device
turns the p-channel pass transistor off.
Reverse Battery Protection
The SiP21102 has a battery reverse protection circuitry that
disconnects the internal circuitry when VIN drops below the
GND voltage. There is no current drawn in such an event.
When the SD pin is hardwired to VIN, the user must connect
the SD pin to VIN via a 100 kΩ resistor if reverse battery
protection is desired. Hardwiring the SD pin directly to the
VIN pin is allowed when reverse battery protection is not
desired.
ERROR
ERROR is an open drain output that goes low when VOUT is
less than 4 % of its normal value. To obtain a logic level
output, connect a pull-up resister from ERROR to VOUT or
any other voltage equal to or less than VIN. ERROR pin is
high impedance (off) when SD pin is low.
Auto-Discharge
VOUT has an internal 100 Ω (typ.) discharge path to ground
when the SD pin is low.
Stability
The circuit is stable with only a small output capacitor equal
to 6 nF/mA (= 1 F at 150 mA). Since the bandwidth of the
error amplifier is around 1-3 MHz and the dominant pole is at
the output node, the capacitor should be capacitive in this
range, i.e., for 150 mA load current, an ESR < 0.4
Ω is
necessary. Parasitic inductance of about 10 nH can be
tolerated.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73213.
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