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參數(shù)資料
| 型號： | SII0680A |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | IDE COMPATIBLE, CD ROM CONTROLLER, PQFP144 |
| 封裝： | LQFP-144 |
| 文件頁數(shù)： | 17/34頁 |
| 文件大?。?/td> | 280K |
| 代理商： | SII0680A |
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SiI 0680A Data Sheet Revision 1.31-1
24
Subject to change without notice
Pin Names: IDE1_CS0_N; IDE1_CS1_N
Pin Numbers: 64, 65
These are the chip select signals from the host used to select the Command Block or Control Block registers. When
IDE1_DMACK_N is asserted, IDE1_CS0_N and IDE1_CS1_N shall be negated and transfers shall be 16 bits wide.
IDE1 Disk Address
Pin Names: IDE1_DA[2..0]
Pin Numbers: 68, 67, 66
Disk Address bits 0 through 2 are normally outputs to the ATA connector to select the register in the drive’s Command Block
register. IDE1_DA [2:0] sends address signals to the secondary channel. These address signals are decoded from the
PCI_AD[2:0] and PCI_CBE[3:0] inputs.
IDE1 Disk I/O Read
Pin Name: IDE1_DIOR_N
Pin Number: 69
This is an active low output which enables data to be read from the drive. The duration and repetition rate of IDE1_DIOR_N
cycles is determined by programming the SiI 0680A PIO timing registers. IDE1_DIOR_N to the secondary channel is driven
high when inactive. This signal is defined as HSTROBE in Ultra DMA write mode to write data to the secondary channel
drive. This signal is also defined as secondary channel HDMARDY_N in Ultra DMA read mode.
IDE1 Disk I/O Write
Pin Name: IDE1_DIOW_N
Pin Number: 70
This is an active low output that enables data to be writte n to the drive. The duration and repetition rate of IDE1_DIOW_N
cycles is determined by programming the SiI 0680A PIO timing registers. IDE1_DIOW_N to the Secondary channel is
driven high when inactive. This signal is also defined as secondary channel STOP in Ultra DMA mode.
IDE1 Cable Detect
Pin Names: IDE1_CBLID_N
Pin Number: 71
IDE1_CBLID_N (Cable Detect) determines the type of cable attached to the primary channel. In general, a low on this pin
indicates that a 40 conductor cable is attached. A h igh indicates that an 80 conductor cable is attached. Refer to the
ATA/ATAPI-6 Specification for complete details.
IDE1 DMA Acknowledge
Pin Name: IDE1_DMACK_N
Pin Number: 74
This signal is normally used by the SiI 0680A in response to IDE1_DMARQ to eith er acknowledge that the secondary
channel is ready to accept data, or that data is available. This signal is also used to write CRC code to the secondary
channel drive at the end of each Ultra DMA burst transfer.
IDE1 Interrupt Request
Pin Name: IDE1_INTRQ
Pin Number: 75
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