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參數(shù)資料
| 型號： | SII0680A |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | IDE COMPATIBLE, CD ROM CONTROLLER, PQFP144 |
| 封裝： | LQFP-144 |
| 文件頁數(shù)： | 15/34頁 |
| 文件大?。?/td> | 280K |
| 代理商： | SII0680A |
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SiI 0680A Data Sheet Revision 1.31-1
22
Subject to change without notice
3.3 SiI 0680A Pin Descriptions
3.3.1 IDE/ATA Primary Channel
IDE0 Disk Data Bus
Pin Names: IDE0_DD[15..0]
Pin Numbers: 25, 24, 23, 22, 21, 20, 19, 18, 15, 14, 13, 12, 11, 10, 9, 8
Disk Data bits 0 through 15 are the 16-bit bi-directional data bus which connects to the ATA device(s). IDE0_DD[15:0] are
data signals to the primary C hannel. IDE0_DD[7:0] defines the low byte while IDE0_DD[15:8] defines the high byte of this
16-bit data register. The data bus is normally in a high impedance state and is driven by the SiI 0680A during the
IDE0_DIOW_N command pulse in either single/multi -word DMA mode, or valid at every edge of IDE0_DIOR_N (HSTROBE)
or IDE0_IORDY (DSTROBE) in Ultra DMA mode. IDE0_DD[7] is a multifunction pin which allows a host to recognize the
absence of an ATA/ATAPI device at power-
l-down resistor be connected to this pin.
IDE0 Chip Select
Pin Names: IDE0_CS0_N; IDE0_CS1_N
Pin Numbers: 28, 29
These are the chip select signals from the host used to select the Command Block or Control Block registers. When
IDE0_DMACK_N is asserted, IDE0_CS0_N and IDE0_CS1_N shall be negated and transfers shall be 16 bits wide.
IDE0 Disk Address
Pin Names: IDE0_DA[2..0]
Pin Numbers: 32, 31, 30
Disk Address bits 0 through 2 are normally outputs to the ATA connector selecting the register in the drive’s Command
Block register. IDE0_DA[2:0] sends address signals to the primary channel. These address signals are decoded from the
PCI_AD[2:0] and PCI_CBE[3:0] inputs.
IDE0 Disk I/O Read
Pin Name: IDE0_DIOR_N
Pin Number: 33
Primary Channel Disk I/O R ead is an active low output which enables data to be read from the drive. The duration and
repetition rate of IDE0_DIOR_N cycles is determined by SiI 0680A programming. IDE0_DIOR_N to the primary channel is
driven high when inactive. This signal is defined as HSTROBE in Ultra DMA write mode to write data to the primary channel
drive. This signal is also defined as primary channel HDMARDY_N in Ultra DMA read mode.
IDE0 Disk I/O Write
Pin Name: IDE0_DIOW_N
Pin Number: 34
Primary Channel Disk I/O Write i s an active low output that enables data to be written to the drive. The duration and
repetition of IDE0_DIOW_N cycles is determined by SiI 0680A Programming. IDE0_DIOW_N to the primary channel is
driven high when inactive. This signal is defined as primary channel STOP in ultra DMA mode.
IDE0 DMA Acknowledge
Pin Name: IDE0_DMACK_N
Pin Number: 35
This signal is normally used by the SiI 0680A in response to IDE0_DMARQ to either acknowledge that the primary channel
is ready to accept data, or that data is available. This signal is also used to write CRC code to the primary channel drive at
the end of each Ultra DMA burst transfer.
IDE0 Cable Detect
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