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參數(shù)資料
| 型號(hào)： | SIC417CD-T1-E3 |
| 廠商： | Vishay Siliconix |
| 文件頁數(shù)： | 11/19頁 |
| 文件大小： | 922K |
| 描述： | IC REG DL BCK/LINEAR SYNC 32MLPQ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | microBUCK® |
| 拓?fù)洌?/td> | 降壓（降壓）同步（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 2 |
| 頻率 - 開關(guān)： | 200kHz ~ 1MHz |
| 電壓/電流 - 輸出 1： | 0.5 V ~ 5.5 V，10A |
| 電壓/電流 - 輸出 2： | 0.75 V ~ 5.25 V，150mA |
| 帶 LED 驅(qū)動(dòng)器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 無 |
| 電源電壓： | 3 V ~ 28 V |
| 工作溫度： | -25°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-PowerWFQFN |
| 供應(yīng)商設(shè)備封裝： | PowerPAK? MLP55-32 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | SIC417CD-T1-E3DKR |
Vishay Siliconix
SiC417
Document Number: 69062
S10-1367-Rev. D, 14-Jun-10
www.vishay.com
11
counter to prepare for soft-start. The SiC417 then begins a
soft-start cycle. The PWM will shut off if V5V falls below
3.6 V.
LDO Regulator
The SiC417 features an integrated LDO regulator with a
programmable output voltage from 0.75 V to 5.25 V using
external resistors, when an external supply is used to power
V5V. The feedback pin (FBL) for the LDO is regulated to 750
mV. There is also an enable pin (ENL) for the LDO that
provides independent control. The LDO voltage can also be
used to provide the bias voltage for the switching regulator,
when V
LDO
is tied to V5V. More detail can be found in the On
Chip LDO bias section coming up.
The LDO output voltage is set by the following equation.
A minimum capacitance of 1 礔 referenced to AGND is
normally required at the output of the LDO for stability. If the
LDO is providing bias power to the device, then a minimum
0.1 礔 capacitor referenced to A
GND
is required along with a
minimum 1.0 礔 capacitor referenced to P
GND
to filter the
gate drive pulses. Refer to the layout guideline section.
LDO Start-up
Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
1. ENL pin
2. V
LDO
output
3. V
IN
input voltage
When the ENL pin is high and V
IN
is above the UVLO point,
the LDO will begin start-up. During the initial phase, when the
LDO output voltage is near zero, the LDO initiates a
current-limited start-up (typically 85 mA) to charge the output
capacitor. When V
LDO
has reached 90 % of the final value
(as sensed at the FBL pin), the LDO current limit is increased
to ~ 200 mA and the LDO output is quickly driven to the
nominal value by the internal LDO regulator.
LDO Switchover Function
The SiC417 includes a switch-over function for the LDO. The
switch-over function is designed to increase efficiency by
using the more efficient dc-to-dc converter to power the LDO
output, avoiding the less efficient LDO regulator when
possible. The switch-over function connects the V
LDO
pin
directly to the V
OUT
pin using an internal switch. When the
switch-over is complete the LDO is turned off, which results
in a power savings and maximizes efficiency. If the LDO
output is used to bias the SiC417, then after switch-over the
device is self-powered from the switching regulator with the
LDO turned off.
The switch-over logic waits for 32 switching cycles before it
starts the switch-over. There are two methods that determine
the switch-over of V
LDO
to V
OUT
.
In the first method, the LDO is already in regulation and the
dc-to-dc converter is later enabled. As soon as the P
GOOD
output goes high, the 32 cycles are started. The voltages at
the V
LDO
and V
OUT
pins are then compared; if the two
voltages are within ?300 mV of each other, the V
LDO
pin
connects to the V
OUT
pin using an internal switch, and the
LDO is turned off.
In the second method, the dc-to-dc converter is already
running and the LDO is enabled. In this case the 32 cycles
are started as soon as the LDO reaches 90 % of its final
value. At this time, the V
LDO
and V
OUT
pins are compared,
and if within ?300 mV the switch-over occurs and the LDO
is turned off.
Benefits of having a switchover circuit
The switchover function is designed to get maximum
efficiency out of the dc-to-dc converter. The efficiency for an
LDO is very low especially for high input voltages. Using the
switchover function we tie any rails connected to V
LDO
through a switch directly to V
OUT
. Once switchover is
complete LDO is turned off which saves power. This gives us
the maximum efficiency out of the SiC417.
If the LDO output is used to bias the SiC417, then after
switchover the V
OUT
self biases the SiC417 and operates in
self-powered mode.
Steps to follow when using the on chip LDO to bias the
SiC417:
" Always tie the V5V to V
LDO
before enabling the LDO
" Enable the LDO before enabling the switcher
" LDO has a current limit of 85 mA at start-up with 12 V
IN
, so
do not connect any load between V
LDO
and ground
" The current limit for the LDO goes up to 200 mA once the
V
LDO
reaches 90 % of its final values and can easily supply
the required bias current to the IC.
Switch-over Limitations on V
OUT
and V
LDO
Because the internal switch-over circuit always compares
the V
OUT
and V
LDO
pins at start-up, there are limitations on
permissible combinations of V
OUT
and V
LDO
. Consider the
case where V
OUT
is programmed to 1.5 V and V
LDO
is
programmed to 1.8 V. After start-up, the device would
connect V
OUT
to V
LDO
and disable the LDO, since the two
voltages are within the ?300 mV switch-over window.
Figure 9 - LDO Start-Up
Figure 10 - LDO Start-Up
V
LDO
R
LDO1
R
LDO2
To FBL pin
V
LDO
= 750 mV x 1+
R
LDO1
R
LDO2
(
)
Constant current startup
V
VLDO
final
90 % of V
VLDO
final
Voltage regulating with
~ 200 mA current limit
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