參數(shù)資料
型號(hào): SI9117
廠商: Vishay Intertechnology,Inc.
英文描述: High-Frequency Converter for Telecom Applications
中文描述: 高頻轉(zhuǎn)換器的電信應(yīng)用
文件頁數(shù): 8/15頁
文件大?。?/td> 132K
代理商: SI9117
Si9117
Vishay Siliconix
www.vishay.com
8
Document Number: 70027
S-40750—Rev. E, 19-Apr-04
FIGURE 1.
Start Circuit
+
+
Transformer Winding
V
CC
To Internal Circuits
+V
IN
V
IN
9.2 V
0.2 V
300 mV
UVLO
C
IN
C
VCC
When power is first applied, the depletion transistor is on, and
current flows from the input capacitor C
IN
into the V
CC
capacitor C
VCC
until V
CC
reaches 9.2 V. The converter
transformer will then supply the V
CC
through a bias winding,
which will raise V
CC
to a level higher than 9.2 V. Ideally this will
be between 11 and 13 V, thus turning off the high-voltage
depletion mode MOSFET. The 9.2-V threshold has a
hysteresis of 300 mV to prevent oscillations when the
transition voltage is not clearly defined or when high-line
supply impedance is encountered.
For applications where the input dc voltage is not high, and the
chip power consumption is not excessive, the feedback
winding can be eliminated. In such cases, the pre-regulator
circuit will behave just like a linear regulator with 9.2-V output
and 10-k series resistance. In this case, the parameters to be
considered are the dropout voltage at lowest line condition and
the power dissipation at highest voltage. The high-voltage
depletion mode MOSFET contains an internal body diode, and
in situations where the V
CC
is being powered from a laboratory
supply, care must be taken to avoid loading the +V
IN
rail
beyond the current rating of this device. Typically, the reverse
characteristics of the device will generate a voltage of 3.4 V on
Pin 11 with 10-k load when powering V
CC
from a lab supply.
In some applications it is necessary to inhibit the start of a
converter until a high enough voltage is present on the supply
bus. This is the case for the following reasons:
Circuitry fed from a high line impedance such as a
telephone line will have difficulty starting, since the
converter will behave like a negative impedance. As the dc
voltage decreases, the input current increases because
constant power is drawn. This causes severe oscillations,
and can in some instances have a destructive effect on the
converter.
During start-up, the Si9117 will begin operation as soon as
the UVLO threshold is reached. Since the converter is de-
signed to operate over a much higher range—for example,
from 36 to 72 V—then between 10 and 36 V input the output
voltage will be out of regulation and undefined. In some
cases, digital circuitry will not accept this mode of operation,
and system faults will be encountered without a RESET
watchdog circuit.
To overcome these problems, a Zener diode of suitable value
V
Z
can be placed in series with the +Vin pin, preventing
start-up until V
Z
+ 9.2 V is reached.
Shutdown
The shutdown pin is configured to allow fast latched
termination of the output pulse. The delay from shutdown to
output is typically 300 ns. This delay is short enough to allow
this pin to be used for over-voltage applications where fast
orderly shutdown is desirable: for example, when control of the
feedback loop is lost.
Using an opto-coupler and a TL431, interface is easy (see
Figure 2). Once latched, the shutdown can only be reset from
the UVLO circuit by re-cycling the power. In the event of an
over-voltage, the latch can be reset by momentarily pulling the
V
CC
to a value lower than the UVLO threshold. This approach
will generally be acceptable, since the feedback winding will
not be supplying power, and the only power maintaining the
latch will be supplied by the depletion start transistor. Note,
however, that this action will still be subject to the power
dissipation limits of the Si9117 package and should ideally be
applied as a short fast pulse.
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