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參數(shù)資料
| 型號(hào)： | SI552 |
| 廠(chǎng)商： | Silicon Laboratories Inc. |
| 英文描述： | DUAL FREQUENCY VCXO (10 MHZ TO 1.4 GHZ) |
| 中文描述： | 雙頻石英振蕩器（10 MHz至1.4 GHz） |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 180K |
| 代理商： | SI552 |
Si552
2
Preliminary Rev. 0.2
1. Electrical Specifications
Table 1. Si552 Electrical Specifications
Parameter
Min
Typ
Max
Units
Notes
Frequency
Nominal Frequency
LVDS/CML/LVPECL
CMOS
10
10
—
—
945
160
MHz
Specified at time of order by P/N.
Also available in bands from
970 to 1134 MHz and 1213 to
1417 MHz.
Initial Accuracy
–1.5
—
1.5
ppm
Measured at +25 °C at time of ship-
ping and at V
C
= V
DD
/2.
Temperature Stability
–20
–50
–100
—
—
—
+20
+50
+100
ppm
Selectable option by P/N. See
Section 4. "Ordering Information" on
page 7. Measured at V
C
= V
DD
/2.
Linearity
BSL
Incremental
–5
–10
±1
±5
+5
+10
%
BSL determined from deviation from
best straight line fit with V
C
ranging
from 10 to 90% of V
DD
. Incremental
slope determined with V
C
ranging
from 10 to 90% of V
DD
.
Tuning Slope (kV) from 10 to
90% of V
DD
—
—
—
180
90
45
—
—
—
ppm/V
Positive slope; selectable option by
P/N. See Section 4. "Ordering Infor-
mation" on page 7.
Modulation Bandwidth
—
10
—
kHz
V
C
Input Impedance
500
—
—
k
Absolute Pull Range (APR)
—
See Notes
—
—
See Section 4. "Ordering Information"
on page 7.
Aging
—
—
±10
ppm
Projected frequency drift over 15 year
life.
Outputs
Symmetry
45
—
55
%
LVPECL: V
DD
– 1.3 V (differential)
LVDS: 1.25 V (differential)
CMOS: V
DD
/2
RMS Jitter for F
OUT
> 500 MHz
Kv = 180 ppm/V
12 kHz to 20 MHz
50 kHz to 80 MHz
Kv = 45, 90 ppm/V
12 kHz to 20 MHz
50 kHz to 80 MHz
—
—
—
—
0.42
0.34
0.28
0.31
—
—
—
—
ps
F
OUT
> 500 MHz
Differential Modes:
LVPECL/LVDS/CML
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