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參數(shù)資料
| 型號： | SI550 |
| 廠商： | Silicon Laboratories Inc. |
| 英文描述： | VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO) 10 MHZ TO 1.4 GHZ |
| 中文描述： | 壓控晶體振蕩器（VCXO）10 MHz至1.4 GHz |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 197K |
| 代理商： | SI550 |
Si550
8
Preliminary Rev. 0.3
3. Ordering Information
The Si550 was designed to support a variety of options including frequency, temperature stability, tuning slope,
output format, and V
DD
. Specific device configurations are programmed into the Si550 at time of shipment.
Configurations are specified using the Part Number Configuration chart shown below. Silicon Labs provides a web
browser-based part number configuration utility to simplify this process. Refer to www.silabs.com/
VCXOPartNumber to access this tool and for further ordering instructions. The Si550 VCXO series is supplied in
an industry-standard, RoHS compliant, lead-free, 6-pad, 5 x 7 mm package. Tape and reel packaging is an
ordering option.
Example Part Number: 550AF622M080BGR is a 5 x 7 mm VCXO in a 6 pad package. The nominal frequency is 622.080 MHz, with
a 3.3 V supply and LVPECL output. Temperature stability is specified as ±50 ppm and the tuning slope is 135 ppm/V. The part is
specified for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format.
DD
3.3
3.3
2.5
2.5
2.5
2.5
1.8
1.8
R = Tape & Reel
Blank = Trays
Operating Temp Range (°C)
G
–40 to +85 °C
Device Revision Letter
2
nd
Option Code
Temperature
Stability
± ppm (max)
100
100
50
50
20
50
Tuning Slope
Kv
ppm/V (typ)
180
90
180
90
45
135
Minimum APR
(±ppm)
@ 2.5 V
75
Note 6
125
30
Note 6
75
Code
A
B
C
D
E
F
Notes:
1. For best jitter and phase noise performance, always choose the smallest Kv that
meets the application’s minimum APR requirements. Unlike SAW-based solutions
which require higher higher Kv values to account for their higher temperature
dependence, the Si55x series provides lower Kv options to minimize noise coupling
and jitter in real-world PLL designs. See AN255 and AN266 for more information.
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with
an APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability, over 15 years.
3. Nominal Pull range (±) = 0.5 x V
DD
x tuning slope.
4. Nominal Absolute Pull Range (
±
APR) = Pull range – stability – lifetime aging
= 0.5 x V
DD
x tuning slope – stability – 10 ppm
5. Minimum APR values noted above include worst case values for all parameters.
6. Combination not available.
@ 3.3 V
100
30
150
80
25
100
@ 1.8 V
25
Note 6
75
25
Note 6
50
550 VCXO
Product Family
1
st
Option Code
Code
A
B
C
D
E
F
G
H
J
K
VDD
3.3
3.3
Output Format
LVPECL
LVDS
CMOS
CML
LVPECL
LVDS
CMOS
CML
CMOS
CML
Notes:
CMOS available to 160 MHz.
Frequency (e.g. 622M080 is 622.080 MHz)
Available frequency range is 10 to 945 MHz, 970 to 1134, and 1213
to 1417 MHz. The position of “M” shifts to denote higher or lower
frequencies.
550
X
X
XXXMXXX
B
G
R
相關(guān)PDF資料 |
PDF描述 |
|---|---|
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| Si5515DC-T1-E3 | SOCKET, FREE, SEALED, 4WAY RoHS Compliant: Yes |
| SI552 | DUAL FREQUENCY VCXO (10 MHZ TO 1.4 GHZ) |
| SI570 | ANY-RATE I2C PROGRAMMABLE XO/VCXO |
| Si571 | ANY-RATE I2C PROGRAMMABLE XO/VCXO |
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|---|---|
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