參數(shù)資料
型號： SI5369D-C-GQ
廠商： SILICON LABORATORIES
元件分類： 時鐘產(chǎn)生/分配
英文描述： 243 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100
封裝： 14 X 14 MM, ROHS COMPLIANT, MS-026AED-HD, TQFP-100
文件頁數(shù)： 21/84頁
文件大小： 870K
代理商： SI5369D-C-GQ
28
Preliminary Rev. 0.4
Reset value = 1110 1101
Register 5.
Bit
D7
D6D5D4
D3D2D1
D0
Name
ICMOS [1:0]
SFOUT2_REG [2:0]
SFOUT1_REG [2:0]
Type
R/W
Bit
Name
Function
7:6
ICMOS [1:0]
ICMOS [1:0].
When the output buffer is set to CMOS mode, these bits determine the output buf-
fer drive strength. The first number below refers to 3.3 V operation; the second to
1.8 V operation. These values assume CKOUT+ is tied to CKOUT-.
00: 8mA/2mA
01: 16 mA/4 mA
10: 24 mA/6 mA
11: 32 mA (3.3 V operation)/8mA (1.8 V operation)
5:3
SFOUT2_REG [2:0] SFOUT2_REG [2:0]
Controls output signal format and disable for CKOUT2 output buffer. The LVPECL
and CMOS output formats draw more current than either LVDS or CML; however,
there are restrictions in the allowed output format pin settings so that the maximum
power dissipation for the TQFP devices is limited when they are operated at 3.3 V.
When there are four enabled LVPECL or CMOS outputs, the fifth output must be
disabled. When there are five enabled outputs, there can be no more than three
outputs that are either LVPECL or CMOS.
000: Reserved
001: Disable
010: CMOS
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
2:0
SFOUT1_REG [2:0] SFOUT1_REG [2:0]
Controls output signal format and disable for CKOUT1 output buffer. The LVPECL
and CMOS output formats draw more current than either LVDS or CML; however,
there are restrictions in the allowed output format pin settings so that the maximum
power dissipation for the TQFP devices is limited when they are operated at 3.3 V.
When there are four enabled LVPECL or CMOS outputs, the fifth output must be
disabled. When there are five enabled outputs, there can be no more than three
outputs that are either LVPECL or CMOS.
000: Reserved
001: Disable
010: CMOS
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SI5369D-C-GQR 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Lo Loop BW Clk Multi Jitter Attn 4In/5Out RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
Si5369-EVB 功能描述:時鐘和定時器開發(fā)工具 SI5369 DEV KIT RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
Si5374B-A-BL 功能描述:時鐘合成器/抖動清除器 Quad DSPLL Jittr Clk Low loop BW 8In/Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
Si5374B-A-GL 功能描述:時鐘合成器/抖動清除器 QUAD DSPLL JITT ATT CLK LO LP BW 8IN/OUT RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
Si5374-EVB 功能描述:時鐘和定時器開發(fā)工具 QUAD DSPLL 8IN/8OUT CLOCK EVAL KIT RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
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