參數(shù)資料
型號: SI5366-C-GQ
廠商: Silicon Laboratories Inc
文件頁數(shù): 14/32頁
文件大小: 0K
描述: IC CLOCK MULTIPLIER PREC 100TQFP
標準包裝: 90
系列: DSPLL®
類型: 時鐘放大器,振動衰減器
PLL:
輸入: 時鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 4:5
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.05GHz
除法器/乘法器: 無/是
電源電壓: 1.71 V ~ 2.75 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP
供應商設備封裝: 100-TQFP(14x14)
包裝: 托盤
Si5366
Rev. 1.0
21
49
LOL
O
LVCMOS
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator.
0 = PLL locked.
1 = PLL unlocked.
50
DBL_FS
I
3-Level
FS_OUT Disable.
This pin performs the following functions:
L = Normal operation. Output path is active and signal format is
determined by SFOUT inputs.
M = CMOS signal format. Overrides SFOUT signal format to
allow FS_OUT to operate in CMOS format while the clock out-
puts operate in a differential output format.
H = Powerdown. Entire FS_OUT divider and output buffer path
is powered down.
This pin has both weak pull-ups and weak pull-downs and
defaults to M.Some designs may require an external resistor
voltage divider when driven by an active device that will tri-
state.
51
CK_CONF
I
LVCMOS
Input Clock Configuration Control.
This pin controls the input clock configuration.
0 = CKIN1, 2, 3, 4 inputs, no FS_OUT alignment.
1 = CKIN1, 3 and CKIN2, 4 clock/FSYNC pairs.
This pin has a weak pull-down.
54
DEC
I
LVCMOS
Coarse Skew Decrement.
A pulse on this pin decreases the input to output device skew
by 1/fOSC (approximately 200 ps). Detailed operations and tim-
ing characteristics for this pin may be found in the Any-Fre-
quency Precision Clock Family Reference Manual. There is no
limit on the range of skew adjustment by this method. If both
INC and DEC are tied high, phase buildout is disabled and the
device maintains a fixed-phase relationship between the
selected input clock and the output clock during an input clock
switch. Detailed operations and timing characteristics for this
pin may be found in the Any-Frequency Precision Clock Family
Reference Manual.
This pin has a weak pull-down.
55
INC
I
LVCMOS
Coarse Skew Increment.
A pulse on this pin increases the input to output skew by 1/fOSC
(approximately 200 ps). Detailed operations and timing charac-
teristics for this pin may be found in the Any-Frequency Preci-
sion Clock Family Reference Manual. There is no limit on the
range of skew adjustment by this method. If both INC and DEC
are tied high, phase buildout is disabled and the device main-
tains a fixed-phase relationship between the selected input
clock and the output clock during an input clock switch.
Detailed operations and timing characteristics for this pin may
be found in the Any-Frequency Precision Clock Family Refer-
ence Manual.
Note: INC does not increase skew if NI_HS = 4.
This pin has a weak pull-down.
Table 8. Si5366 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
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