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參數(shù)資料
| 型號(hào)： | SI5364-F-BC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SONET/SDH PRECISION PORT CARD CLOCK IC |
| 中文描述： | SONET / SDH的精密端口卡時(shí)鐘IC |
| 文件頁數(shù)： | 27/40頁 |
| 文件大?。?/td> | 565K |
| 代理商： | SI5364-F-BC |
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Si5364
Rev. 2.2
27
E2
E1
REF/CLKIN_F+
REF/CLKIN_F–
I*
AC Coupled
200–500 mV
PPD
(See Table 2)
Frequency Reference/Backup Clock Input.
Used by the DSPLL as a frequency reference for
determining the frequency accuracy of the CLKIN_A
and CLKIN_B inputs. If the frequency offset of either
the CLKIN_A or the CLKIN_B inputs relative to REF/
CLKIN_F exceeds the selected frequency offset
threshold, the corresponding Frequency Offset error
flag (FOS_A or FOS_B) is asserted. The frequency
offset threshold is selected with the SMC/S3N input.
In automatic switching mode, Frequency Offset
errors can cause switching of the input clock selec-
tion. (See AUTOSEL pin description.) If the REF/
CLKIN_F signal is not present, the FOS_A and
FOS_B error flags are generated, along with the
LOS_F Loss-of-Signal error flag. The FOS_A and
FOS_B error flags are ignored for the purposes of
automatic switching in the presence of the LOS_F
flag.
The REF/CLKIN_F input can also be utilized as a
third clock input that can be selected by the DSPLL
in the generation of the SONET/SDH compliant clock
outputs. When REF/CLKIN_F is input to the DSPLL
rather than as a frequency accuracy reference for
CLKIN_A and CLKIN_B, the FOS_A or FOS_B fre-
quency offset error outputs can be disabled with the
DSBLFOS control input.
The frequencies of the Si5364 clock outputs are
each a 1, 8, or 32x multiple of the frequency of the
selected clock input. The multiplication ratio is
selected using Frequency Select (FRQSEL) control
pins associated with each clock output. An additional
scaling factor of either 238/255 or 255/238 can be
selected for FEC operation using the FEC[1:0] con-
trol pins.
The clock input frequency is nominally 19.44 MHz.
Clock input frequency can be varied over the range
indicated in Table 3 on page 8 to produce other out-
put frequencies.
F10
LOS_A
O
LVTTL
Loss-of-Signal (LOS) Alarm for CLKIN_A.
Indicates that the Si5364 detects a missing pulse on
the CLKIN_A clock input signal. The LOS alarm is
cleared after either 100
ms
or 13 s of valid CLKIN_A
clock input signal, depending on the setting of the
VALTIME control input.
E10
LOS_B
O
LVTTL
Loss-of-Signal (LOS) Alarm for CLKIN_B.
See LOS_A.
Table 10. Pin Descriptions (Continued)
I/O
Signal Level
Pin #
Pin Name
Description
*Note:
The LVTTL inputs on the Si5364 device have an internal pulldown mechanism that causes the input to default to a logic
low state if the input is not driven from an external source.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5364-G-BC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precision Port Card 19 155 622 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5364-H-BL | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Prcsn Port Card Clock Multiplr RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5364-H-BLR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precision 19MHz 155MHz 622MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5364-H-GL | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Prcsn Port Card Clock Multiplr RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5364-H-GLR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precision 19MHz 155MHz 622MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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