參數(shù)資料
型號： SI5351B-A-GU
廠商： Silicon Laboratories Inc
文件頁數(shù)： 14/72頁
文件大?。?/td> 0K
描述： IC CLK GEN PLL BLANK CUST 24QSOP
標(biāo)準(zhǔn)包裝： 56
系列： MultiSynth™
類型： *
PLL： 是
輸入： 晶體
輸出： CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:8
差分 - 輸入:輸出： 無/無
頻率 - 最大： 133MHz
除法器/乘法器： 是/無
電源電壓： 2.25 V ~ 3.63 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 24-QSOP
包裝： 管件
Si5351A/B/C
Preliminary Rev. 0.95
21
6. Design Considerations
The Si5351 is a self-contained clock generator that requires very few external components. The following general
guidelines are recommended to ensure optimum performance. Refer to “AN554: Si5350/51 PCB Layout Guide” for
additional layout recommendations.
6.1. Power Supply Decoupling/Filtering
The Si5351 has built-in power supply filtering circuitry and extensive internal Low Drop Out (LDO) voltage
regulators to help minimize the number of external bypass components. All that is recommended is one 0.1 F
decoupling capacitor per power supply pin. This capacitor should be mounted as close to the VDD and VDDOx
pins as possible without using vias.
6.2. Power Supply Sequencing
The VDD and VDDOx (i.e., VDDO0, VDDO1, VDDO2, VDDO3) power supply pins have been separated to allow
flexibility in output signal levels. If a minimum output-to-output skew is important, then all VDDOx must be applied
before VDD. Unused VDDOx pins should be tied to VDD.
6.3. External Crystal
The external crystal should be mounted as close to the pins as possible using short PCB traces. The XA and XB
traces should be kept away from other high-speed signal traces. See “AN551: Crystal Selection Guide” for more
details.
6.4. External Crystal Load Capacitors
The Si5351 provides the option of using internal and external crystal load capacitors. If internal load capacitance is
insufficient, capacitors of value < 2 pF may be used to increased equivalent load capacitance. If external load
capacitors are used, they should be placed as close to the XA/XB pads as possible. See AN554 for more details.
6.5. Unused Pins
Unused voltage control pin should be tied to GND.
Unused CLKIN pin should be tied to GND.
Unused XA/XB pins should be left floating. Refer to "5.6. Replacing a Crystal with a Clock" on page 20 when using
XA as a clock input pin.
Unused output pins (CLK0–CLK7) should be left floating.
Unused VDDOx pins should be tied to VDD.
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