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參數(shù)資料
| 型號： | SI5321-H-BL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 14/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK MULT SONET/SDH 63-PBGA |
| 標準包裝： | 260 |
| 系列： | DSPLL® |
| 類型： | 時鐘乘法器 |
| PLL： | 是 |
| 輸入： | LVTTL |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.8GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -20°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 63-LBGA |
| 供應商設備封裝： | 63-PBGA（9x9） |
| 包裝： | 托盤 |
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Si5321
Rev. 2.5
21
detected. When the input clock returns and is validated,
the device exits digital hold mode by re-locking to the
input clock without executing another self-calibration.
2.9. Bias Generation Circuitry
The Si5321 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents, which significantly
reduces power consumption and variation as compared
with traditional implementations that use an internal
resistor. The bias generation circuitry requires a 10 k
Ω
(1%) resistor connected between REXT and GND.
2.10. Differential Input Circuitry
The Si5321 provides a differential input for the clock
input, CLKIN. This input is internally-biased to a voltage
differential
or
single-ended
driver
circuit.
For
transmission line termination, the termination resistor is
connected externally as shown.
2.11. Differential Output Circuitry
The Si5321 utilizes a current mode logic (CML)
architecture to drive the differential clock output,
CLKOUT.
For single-ended output operation simply connect to
either CLKOUT+ or CLKOUT– and leave the unused
signal unconnected.
2.12. Power Supply Connections
The Si5321 incorporates an on-chip voltage regulator to
power the device from a 3.3 V supply. The voltage
regulator requires an external compensation circuit of
one resistor and one capacitor to ensure stability over
all operating conditions.
Internally, the Si5321 VDD33 pins are connected to the
on-chip voltage regulator input and to the device’s
LVTTL I/O circuitry. The VDD25 pins supply power to the
core DSPLL circuitry, and are also used for connection
of the external compensation circuit.
The regulator’s compensation circuit is a resistor and a
capacitor in series between the VDD25 node and ground.
Typically, the resistor is incorporated into the capacitor’s
equivalent series resistance (ESR). The target RC time
constant for this combination is 15 to 50
μs. The
capacitor used in the Si5321 evaluation board is a 33
μf
tantalum capacitor with an ESR of 0.8
Ω. This gives an
RC time constant of 26.4
μs. The Venkel part number
TA6R3TCR336KBR is an example of a capacitor that
meets these specifications. (See Figure 5.)
To get optimal performance from the Si5321 device, the
power supply noise spectrum must comply with the plot
in Figure 9. This plot shows the power supply noise
tolerance mask for the Si5321. The customer should
provide a 3.3 V supply that does not have noise density
in excess of the amount shown in the diagram.
However, the diagram cannot be used as spur criteria
for a power supply that contains single tone noise.
Figure 9. Power Supply Noise Tolerance Mask
f
Vn (μV/√Hz)
2100
42
10 kHz
500 kHz
100 Mhz
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| Si5321-H-GL | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precisn Clock Multiplr RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5321-H-ZL2 | 制造商:Silicon Laboratories Inc 功能描述: |
| Si5321-XLNX-DC | 功能描述:子卡和OEM板 Silabs/Xilinx Ref Design RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| SI5322 | 制造商:SILABS 制造商全稱:SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock |
| Si5322/23-EVB | 功能描述:時鐘和定時器開發(fā)工具 Si5322/Si5323 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
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