參數(shù)資料
型號(hào): SI5321-H-BL
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 10/34頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK MULT SONET/SDH 63-PBGA
標(biāo)準(zhǔn)包裝: 260
系列: DSPLL®
類(lèi)型: 時(shí)鐘乘法器
PLL:
輸入: LVTTL
輸出: CML
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.8GHz
除法器/乘法器: 是/是
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -20°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 63-LBGA
供應(yīng)商設(shè)備封裝: 63-PBGA(9x9)
包裝: 托盤(pán)
Si5321
18
Rev. 2.5
The Si5321 clock input frequencies are variable within
the range specified in Table 3 on page 7. The output
rates are scaled accordingly. If a 19.44 MHz input clock
is used, the clock output frequency is 19.44, 38.88,
77.76, 155.52 MHz, etc.
2.2.1. FEC Rate Conversion
The Si5321 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x,
1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock frequency
multiplication function with an option for additional
forward or reverse frequency scaling by a factor of 255/
238 (15/14), 255/237 (85/79), or 66/64 (33/32) for FEC
rate conversion applications. The 255/237 and the 66/
64 rate conversions requires the input clock rate to be in
the 155 MHz or higher ranges. The multiplication factor
is configured by selecting the input and output clock
frequency ranges for the device. The additional
frequency scaling for FEC rate conversion is selected
using the FEC[2:0] control inputs.
For example, a 622.08 MHz output clock (a non-FEC
rate) can be generated from a 19.44 MHz input clock (a
non-FEC
rate)
by
setting
INFRQSEL[2:0] = 001
(19.44 MHz range), setting FRQSEL[2:0] = 011 (32x
multiplication) and setting FEC[2:0] = 000 (no FEC
scaling). A 666.51 MHz output clock (an FEC rate) can
be generated from a 19.44 MHz input clock (a non-FEC
rate) by setting INFRQSEL[2:0] = 001 (19.44 MHz
range), setting FRQSEL[2:0] = 011 (32x multiplication)
Table 7. Loop Bandwidth and FEC Settings
External Inputs
Effective
FEC
Conversion
Rate
Effective
PLL
Bandwidth
(Hz)
BWBOOST
BWSEL
[1:0]
FEC
[2:0]
0
00
000
001
010
011
100
101
110
111
1/1
255/238
238/255
Reserved
255/237
237/255
66/64
64/66
3200
3200
0
10
000
001
010
011
100
101
110
111
1/1
255/238
238/255
Reserved
255/237
237/255
66/64
64/66
800
800
0
11
000
001
010
011
100
101
110
111
1/1
255/238
238/255
Reserved
255/237
237/255
66/64
64/66
6400
6400
1
00
10
11
01
0xx
1/1
6400
1600
12800
3200
0
01
000
001
010
011
100
101
110
111
1/1
255/238
238/255
Reserved
255/237
237/255
66/64
64/66
1600
1600
Table 8. Nominal Clock Input Frequencies
Input Clock
Frequency
Range
INFRQSEL2 INFRQSEL1 INFRQSEL0
Reserved
111
622 MHz
110
311 MHz
101
155 MHz
100
77 MHz
011
38 MHz
010
19 MHz
001
Reserved
000
Table 9. Nominal Clock Output Frequencies
Output Clock
Frequency
Range
FRQSEL2
FRQSEL1
FRQSEL0
2,488.32 MHz
1
1244.16 MHz
1
0
622.08 MHz
0
1
311.04 MHz
1
0
1
155.52 MHz
0
1
0
77.76 MHz
1
0
38.88 MHz
0
19.44 MHz
0
1
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