參數(shù)資料
型號(hào)： SI5320-H-GL
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 13/34頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK MULT SONET/SDH 63LFBGA
標(biāo)準(zhǔn)包裝： 260
系列： DSPLL®
類(lèi)型： 時(shí)鐘乘法器
PLL： 是
輸入： LVTTL
輸出： CML
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 693MHz
除法器/乘法器： 是/是
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -20°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 63-LBGA
供應(yīng)商設(shè)備封裝： 63-PBGA（9x9）
包裝： 托盤(pán)
Si5320
20
Rev. 2.5
2.9. Bias Generation Circuitry
The Si5320 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces power consumption and variation as compared
with traditional implementations that use an internal
resistor. The bias generation circuitry requires a 10 k
Ω
(1%) resistor connected between REXT and GND.
2.10. Differential Input Circuitry
The Si5320 provides a differential input for the clock
input, CLKIN. This input is internally biased to a voltage
of VICM (see Table 2 on page 6) and may be driven by a
differential or single-ended driver circuit. For differential
transmission lines, the termination resistor is connected
externally as shown.
2.11. Differential Output Circuitry
The Si5320 utilizes a current mode logic (CML)
architecture to drive the differential clock output,
CLKOUT.
For single-ended output operation, simply connect to
either CLKOUT+ or CLKOUT–, and leave the unused
signal unconnected.
2.12. Power Supply Connections
The Si5320 incorporates an on-chip voltage regulator.
The
voltage
regulator
requires
an
external
compensation circuit of one resistor and one capacitor
to ensure stability over all operating conditions.
Internally, the Si5320 VDD33 pins are connected to the
on-chip voltage regulator input, and the VDD33 pins also
supply power to the device’s LVTTL I/O circuitry. The
VDD25 pins supply power to the core DSPLL circuitry
and are also used for connection of the external
compensation circuit.
The regulator’s compensation circuit is in reality a
resistor and a capacitor in series between the VDD25
node and ground. (See Figure 5 on page 15.) Typically,
the resistor is incorporated into the capacitor’s
equivalent series resistance (ESR). The target RC time
constant for this combination is 15 to 50
μs. The
capacitor used in the Si5320 evaluation board is a
33
μF tantalum capacitor with an ESR of 0.8 Ω. This
gives an RC time constant of 26.4
μs. The Venkel part
number, TA6R3TCR336KBR, is an example of a
capacitor that meets these specs.
To get optimal performance from the Si5320 device, the
power supply noise spectrum must comply with the plot
in Figure 10. This plot shows the power supply noise
tolerance mask for the Si5320. The customer should
provide a 3.3 V supply that does not have noise density
in excess of the amount shown in the diagram.
However, the diagram cannot be used as spur criteria
for a power supply that contains single tone noise.
Figure 10. Power Supply Noise Tolerance Mask
f
Vn (μV/√Hz)
2100
42
10 kHz
500 kHz
100 Mhz
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