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參數(shù)資料
| 型號： | SI5320-H-BL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 9/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK MULT SONET/SDH 63-PBGA |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 系列： | DSPLL® |
| 類型： | 時鐘乘法器 |
| PLL： | 是 |
| 輸入： | LVTTL |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 693MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -20°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 63-LBGA |
| 供應(yīng)商設(shè)備封裝： | 63-PBGA（9x9） |
| 包裝： | 托盤 |
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Si5320
Rev. 2.5
17
2.2.1. FEC Rate Conversion
The Si5320 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x,
1x, 2x, 4x, 8x, 16x, or 32x clock frequency multiplication
function with an option for additional frequency scaling
by a factor of 255/238 or 238/255 for FEC rate
compatibility. The multiplication factor is configured by
selecting the input and output clock frequency ranges
for the device. The additional frequency scaling by a
factor of either 255/238 or 238/255 for FEC compatibility
is selected using the FEC[1:0] control inputs. (See
For example, a 622.08 MHz output clock (a non-FEC
rate) can be generated from a 19.44 MHz input clock (a
non-FEC
rate)
by
setting
INFRQSEL[2:0] = 001
(19.44 MHz range), setting FRQSEL [1:0] = 11 (32x
multiplication), and setting FEC[1:0] = 00 (no FEC
scaling).
A 666.51 MHz output clock (a FEC rate) can be
generated from a 19.44 MHz input clock (a non-FEC
rate) by setting INFRQSEL[2:0] = 001 (19.44 MHz
range), setting FRQSEL [1:0] = 11 (32x multiplication),
and setting FEC[1:0] = 01 (255/238 FEC scaling).
Finally, a 622.08 MHz output clock (a non-FEC rate) can
be generated from a 20.83 MHz input clock (a FEC rate)
by setting INFRQSEL[2:0] = 001 (19.44 MHz range),
setting FRQSEL [1:0] = 11 (32x multiplication), and
setting FEC[1:0] = 10 (238/255 FEC scaling).
2.3. PLL Performance
The Si5320 PLL is designed to provide extremely low
jitter generation, high jitter tolerance, and a well-
controlled jitter transfer function with low peaking and a
high degree of jitter attenuation.
2.3.1. Jitter Generation
Jitter generation is defined as the amount of jitter
produced at the output of the device with a jitter free
input clock. Generated jitter arises from sources within
the VCO and other PLL components. Jitter generation is
also a function of the PLL bandwidth setting. Higher
loop bandwidth settings may result in lower jitter
generation, but may also result in less attenuation of
jitter on the input clock signal.
2.3.2. Jitter Transfer
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter for a specified jitter frequency. The
jitter transfer characteristic determines the amount of
input clock jitter that passes to the outputs. The DSPLL
technology used in the Si5320 provides tightly-
controlled jitter transfer curves because the PLL gain
parameters are determined by digital circuits that do not
vary over supply voltage, process, and temperature. In
a system application, a well-controlled transfer curve
Table 7. Loop Bandwidth Settings
Loop Bandwidth BWSEL1
BWSEL0
DBLBW*
12800 Hz
1
6400 Hz
1
0
6400 Hz
0
1
3200 Hz
0
3200 Hz
0
1
1600 Hz
0
1
0
1600 Hz
1
0
1
800 Hz
1
0
*Note: When DBLBW = 1, FXDDELAY must be asserted and
FEC scaling must be disabled.
Table 8. Nominal Clock Input Frequencies
Input Clock
Frequency
Range
INFRQSEL2 INFRQSEL1 INFRQSEL0
Reserved
111
622 MHz
110
311 MHz
101
155 MHz
100
77 MHz
011
38 MHz
010
19 MHz
001
Reserved
000
Table 9. Nominal Clock Output Frequencies
Output Clock Frequency
Range
FRQSEL1
FRQSEL0
622 MHz
1
155 MHz
1
0
19 MHz
0
1
Driver Powerdown
0
Table 10. FEC Frequency Scalings
FEC Frequency
Scaling
FEC1
FEC0
1/1
0
255/238
0
1
238/255
1
0
Reserved
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SI5320-H-GL | IC CLOCK MULT SONET/SDH 63LFBGA |
| SI5321-G-BC | IC PREC CLOCK MULTIPLIER 63CBGA |
| SI5321-H-BL | IC CLOCK MULT SONET/SDH 63-PBGA |
| SI5322-B-GM | IC PREC CLOCK MULTIPLIER 36QFN |
| SI5323-B-GM | IC MULTIPLIER/ATTENUATOR 36QFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Si5320-H-GL | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precisn Clock Multiplr RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5320-X-BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SONET/SDH PRECISION CLOCK MULTIPLIER IC |
| SI5321 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SONET/SDH PRECISION CLOCK MULTIPLIER IC |
| SI5321-EVB | 功能描述:時鐘和定時器開發(fā)工具 G.709FEC & 66/64Sc 19-2.5GHz Output RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5321-F-BC | 功能描述:時鐘合成器/抖動清除器 FOR NEW DESIGNS RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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