JGEN(PP) 12 kHz to 20 MHz — 6.8 10." />
參數(shù)資料
型號: SI5320-H-BL
廠商: Silicon Laboratories Inc
文件頁數(shù): 3/34頁
文件大?。?/td> 0K
描述: IC CLOCK MULT SONET/SDH 63-PBGA
標準包裝: 260
系列: DSPLL®
類型: 時鐘乘法器
PLL:
輸入: LVTTL
輸出: CML
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 693MHz
除法器/乘法器: 是/是
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -20°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 63-LBGA
供應商設備封裝: 63-PBGA(9x9)
包裝: 托盤
Si5320
Rev. 2.5
11
CLKOUT Peak-Peak Jitter Generation
FEC[1:0] = 00
JGEN(PP)
12 kHz to 20 MHz
6.8
10.0
ps
50 kHz to 80 MHz
3.7
5.0
ps
Jitter Transfer Bandwidth (see Figure 6)
FBW
BW = 3200 Hz
3200
Hz
Wander/Jitter Transfer Peaking
JP
< 3200 Hz
0.05
0.1
dB
Wander/Jitter at 3200 Hz Bandwidth
(BWSEL[1:0] = 00 and DBLBW = 0)
Jitter Tolerance (see Figure 7)
JTOL(PP)
f= 32 Hz
1000
—ns
f= 320Hz
100
—ns
f = 3200 Hz
10
—ns
CLKOUT RMS Jitter Generation
FEC[1:0] = 00
JGEN(RMS)
12 kHz to 20 MHz
0.86
1.2
ps
50 kHz to 80 MHz
0.29
0.4
ps
CLKOUT RMS Jitter Generation
FEC[1:0] = 01, 10
JGEN(RMS)
12 kHz to 20 MHz
0.79
1.2
ps
50 kHz to 80 MHz
0.28
0.4
ps
CLKOUT Peak-Peak Jitter Generation
FEC[1:0] = 00
JGEN(PP)
12 kHz to 20 MHz
7.7
10.0
ps
50 kHz to 80 MHz
3.9
5.0
ps
CLKOUT Peak-Peak Jitter Generation
FEC[1:0] = 01, 10
JGEN(PP)
12 kHz to 20 MHz
7.2
10.0
ps
50 kHz to 80 MHz
4.0
5.0
ps
Jitter Transfer Bandwidth (see Figure 6)
FBW
BW = 3200 Hz
3200
—Hz
Wander/Jitter Transfer Peaking
JP
< 3200 Hz
0.05
0.1
dB
Wander/Jitter at 6400 Hz Bandwidth
(BWSEL[1:0] = 00 and DBLBW = 1)
Jitter Tolerance (see Figure 7)
f = 64 Hz
500
ns
f= 640Hz
50
ns
f= 6400 Hz
5
ns
CLKOUT RMS Jitter Generation
FEC[1:0] = 00
JGEN(RMS)
12 kHz to 20 MHz
0.7
1.0
ps
50 kHz to 80 MHz
0.25
0.3
ps
CLKOUT Peak-Peak Jitter Generation
FEC[1:0] = 00
JGEN(PP)
12 kHz to 20 MHz
6.6
9.0
ps
50 kHz to 80 MHz
3.8
5.0
ps
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of
nanoseconds per millisecond. The equivalent ps/
μs unit is used here since the maximum phase transient magnitude for the
Si5320 (tPT_MTIE) never reaches one nanosecond.
相關PDF資料
PDF描述
SI5320-H-GL IC CLOCK MULT SONET/SDH 63LFBGA
SI5321-G-BC IC PREC CLOCK MULTIPLIER 63CBGA
SI5321-H-BL IC CLOCK MULT SONET/SDH 63-PBGA
SI5322-B-GM IC PREC CLOCK MULTIPLIER 36QFN
SI5323-B-GM IC MULTIPLIER/ATTENUATOR 36QFN
相關代理商/技術參數(shù)
參數(shù)描述
Si5320-H-GL 功能描述:時鐘發(fā)生器及支持產品 SONET/SDH Precisn Clock Multiplr RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
SI5320-X-BC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SONET/SDH PRECISION CLOCK MULTIPLIER IC
SI5321 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SONET/SDH PRECISION CLOCK MULTIPLIER IC
SI5321-EVB 功能描述:時鐘和定時器開發(fā)工具 G.709FEC & 66/64Sc 19-2.5GHz Output RoHS:否 制造商:Texas Instruments 產品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
SI5321-F-BC 功能描述:時鐘合成器/抖動清除器 FOR NEW DESIGNS RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel