
Si5317
Rev. 1.1
5
Differential Input
Voltage Swing
VID
fCKIN < 212.5 MHz
0.2
—
VPP
fCKIN > 212.5 MHz
0.25
—
VPP
Common Mode
VOCM
LVPECL 100
load
line-to-line
VDD –
1.42
—VDD –
1.25
V
Differential Output Swing
VOD
LVPECL 100
load
line-to-line
1.1
—
1.9
VPP
Single-ended Output Swing
VSE
LVPECL 100
load
line-to-line
0.5
—
0.93
VPP
Differential Output Voltage
CKOVD
CML 100
load
line-to-line
350
425
500
mVPP
Common Mode
Output Voltage
CKOVCM
CML 100
load
line-to-line
—VDD –
0.36
—V
Differential
Output Voltage
CKOVD
LVDS 100
load
line-to-line
500
700
900
mVPP
Low swing LVDS 100
load
line-to-line
350
425
500
mVPP
Common Mode
Output Voltage
CKOVCM
LVDS 100
load
line-to-line
1.125
1.2
1.275
V
Output Voltage Low
CKOVOLLH
CMOS
—
0.4
V
Output Voltage High
CKOVOHLH
VDD = 1.71 V
CMOS
0.8 x VDD
——
V
Output Drive Current
CKOIO
CMOS
Driving into CKOVOL for out-
put low or CKOVOH for output
high. CKOUT+ and CKOUT–
shorted externally.
VDD = 1.8 V
—
7.5
—
mA
VDD = 3.3 V
—
32
—
mA
2-Level LVCMOS Input Pins
Input Voltage Low
VIL
VDD =1.71V
—
0.5
V
VDD =2.25V
—
0.7
V
VDD =2.97V
—
0.8
V
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Notes:
1. LVPECL outputs require VDD > 2.25 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
3. No overshoot or undershoot.