參數(shù)資料
型號: SI51211-A01AFM
廠商: Silicon Laboratories Inc
文件頁數(shù): 10/12頁
文件大小: 0K
描述: IC CLK GEN FACTORY CONFIG 8TDFN
標準包裝: 100
類型: *
PLL: 帶旁路
輸入: 時鐘,晶體
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:3
差分 - 輸入:輸出: 無/無
頻率 - 最大: 200MHz
除法器/乘法器: 是/無
電源電壓: 2.375 V ~ 3.63 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-WFDFN 裸露焊盤
供應商設備封裝: 8-TDFN(1.4x1.6)
包裝: 管件
Si51211
Preliminary Rev. 0.7
7
3. Functional Description
3.1. Input Frequency Range
The input frequency range is from 8.0 to 48.0 MHz for crystals and ceramic resonators. If an external clock is used,
the input frequency range is from 8.0 to 166.0 MHz.
3.2. Output Frequency Range and Outputs
Up to three outputs can be programmed as SSCLK or REFCLK. SSCLK output can be synthesized to any value
from 3 to 200 MHz with spread based on valid input frequency. The spread at SSCLK pins can be stopped by the
SSON input control pin. If SSON pin is high (VDD), the frequency at SSCLK pin is synthesized to the nominal value
of the input frequency and there is no spread.
REFCLK is the buffered output of the oscillator and is the same frequency as the input frequency without spread.
However, REFCLK_D output is divided by output dividers from 2 to 32. By using only low cost, fundamental mode
crystals, the Si51211 can synthesize output frequency up to 200 MHz, eliminating the need for higher order
crystals (Xtals) and crystal oscillators (XOs). This reduces the cost while improving the system clock accuracy,
performance, and reliability.
3.3. Programmable Modulation Frequency
The spread spectrum clock (SSC) modulation default value is 31.5 kHz. The higher values of up to 62 kHz can also
be programmed. Less than 30 kHz modulation frequency is not recommended to stay out of the range audio
frequency bandwidth since this frequency could be detected as a noise by the audio receivers within the vicinity.
3.4. Programmable Spread Percent (%)
The spread percent (%) value is programmable from ±0.25% to ±1% (center spread) for all SSCLK frequencies. It
is possible to program smaller or larger non-standard values of spread percentage. Contact Silicon Labs if these
non-standard spread percent values are required in the application.
3.5. SSON or Frequency Select (FSEL)
The Si51211 pin 4 and 6 can be programmed as either SSON to enable or disable the programmed spread percent
value or as frequency select (FSEL). If SSON is used, when this pin is pulled high (VDD), the spread is stopped
and the frequency is the nominal value without spread. If low (GND), the frequency is the nominal value with the
spread.
If FSEL function is used, the output pins can be programmed for different set of frequencies as selected by FSEL.
SSCLK value can be any frequency from 3 to 200 MHz, but the spread % is the same percent value. REFCLK is
the same frequency as the input reference clock and the REFCLK_D input clock is divided by 2 to 32 without
spread. The set of frequencies in Table 4 is given as an example, using a 48 MHz crystal.
3.6. Power Down (PD) or Output Enable (OE)
The Si51211 pin 6 can be programmed as PD input. Pin 4 and pin 6 can be programmed as OE input. PD turns off
both PLL and output buffers whereas OE only disables the output buffers to Hi-Z.
Table 4. Example Frequencies
FSEL
(Pin 6)
SSCLK1
(Pin 4)
066 MHz, ±1%
133 MHz, ±1%
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