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參數(shù)資料
| 型號(hào)： | SI51210-A01AFM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN FACTORY CONFIG 6TDFN |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | 時(shí)鐘，晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 2.375 V ~ 3.63 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-WFDFN |
| 供應(yīng)商設(shè)備封裝： | 6-TDFN（1.2x1.4） |
| 包裝： | 管件 |
Si51210
6
Preliminary Rev. 0.7
2. Design Considerations
2.1. Typical Application Schematic
2.2. Comments and Recommendations
Decoupling Capacitor:
A decoupling capacitor of 0.1 μF must be used between VDD and VSS on pin 1. Place the
capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin
and to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the
VDD pin. In addition, a 10 F capacitor should be placed between VDD and VSS.
Series Termination Resistor
: A series termination resistor is recommended if the distance between the outputs
(SSCLK or REFCLK pins) and the load is over 1 inches. The nominal impedance of the SSCLK output is about
30 . Use a 20 resistor in series with the output to terminate a 50 trace impedance and place a 20 resistor
as close to the SSCLK output as possible.
Crystal and Crystal Load:
Only use a parallel resonant fundamental AT cut crystal. Do not use higher overtone
crystals.
To meet the crystal initial accuracy specification (in ppm) make sure that external crystal load capacitor is
matched to crystal load specification. To determine the value of CL1 and CL2, use the following formula:
C1 = C2 = 2CL – (Cpin + Cp)
Where: CL is load capacitance stated by crystal manufacturer
Cpin is the Si51210 pin capacitance (4 pF).
Cp is the parasitic capacitance of the PCB traces.
Example:
If a crystal with CL = 12 pF specification is used and Cp = 1 pF (parasitic PCB capacitance on PCB), 19
or 20 pF external capacitors from pins XIN (pin 2) and XOUT (Pin 3) to VSS are required. Users must verify Cp
value.
VDD
VSS
XOUT
XIN
FSEL
SSCLK3
VDD
Si51210
0.1F
10F
CL1
CL2
VDD
5K
XIN
XOUT
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| Si51210-A01AFMR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 6 TDFN micro-Clock fact config clk gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si51211-A01AFM | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 8 TDFN microClockgen SL Clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si51211-A01AFMR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 8 TDFN micro-Clock fact config clk gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI51211-A19AFM | 制造商:Silicon Laboratories Inc 功能描述:8 TDFN MICRO-CLOCK, FACTORY CONFIGURABLE CLOCK GENERATOR - Bulk |
| SI51211-EVB | 功能描述:Si51210, Si51211, Si51214 - Timing, Clock Generator Evaluation Board 制造商:silicon labs 系列:- 零件狀態(tài):有效 主要用途:計(jì)時(shí)，時(shí)鐘發(fā)生器 嵌入式:- 使用的 IC/零件:Si51210，Si51211，Si51214 主要屬性:- 輔助屬性:- 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
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