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參數(shù)資料
| 型號： | SI5023-D-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECVRY W/AMP 28MLP |
| 標(biāo)準包裝： | 60 |
| 系列： | DSPLL® |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR） |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，ATM 應(yīng)用 |
| 輸入： | 時鐘 |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-QFN（5x5） |
| 包裝： | 管件 |
| 其它名稱： | 336-1276 |
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Si5023
24
Rev. 1.3
19
RESET/CAL
I
LVTTL
Reset/Calibrate.
Driving this input high for at least 1
μs will reset
internal device circuitry. A high to low transition on
this pin will force a DSPLL calibration. For normal
operation, drive this pin low.
Note: This input has a weak internal pulldown.
20
REXT
External Bias Resistor.
This resistor is used to establish internal bias cur-
rents within the device. This pin must be connected
through a 10 k
Ω (1%) resistor to GND.
22
23
CLKOUT–
CLKOUT+
OCML
Differential Clock Output.
The output clock is recovered from the data signal
present on DIN except when LTR is asserted or the
LOL state has been entered.
24
CLKDSBL
I
LVTTL
Clock Disable.
When this input is high, the CLKOUT output drivers
are disabled. For normal operation, this pin should
be low.
Note: This input has a weak internal pulldown.
26
BER_LVL
I
Bit Error Rate Level Control.
The BER threshold level is set by applying a volt-
age to this pin. The applied voltage is as described
in the BER_LVL section. When the BER exceeds
the programmed threshold, BER_ALM is driven low.
If this pin is tied to GND, BER_ALM is disabled.
27
BER_ALM
OLVTTL
Bit Error Rate Alarm.
This pin will be driven low to indicate that the BER
threshold set by BER_LVL has been exceeded.
There is no hysteresis.
28
BERMON
O
Bit Error Rate Monitor.
The voltage on this pin is proportional to the
detected bit error rate computed by the internal
BER processor. This voltage output has a range of
0 to 0.87 V. See Figure 8 on page 15.
The output is a current source, which requires a
5k
Ω (1%) resistor to GND to guarantee the operat-
ing range shown in Figure 8. This pin may be left
unconnected.
GND Pad
GND
Supply Ground.
Nominally 0.0 V. The 3 x 3 mm square GND pad
found on the bottom of the 28-lead micro leaded
package (see Figure 22) must be connected
directly to supply ground. Minimize the ground path
inductance for optimal performance.
Table 9. Si5023 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
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