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參數(shù)資料
| 型號： | SI5010-B-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY LP 20-QFN |
| 標準包裝： | 75 |
| 系列： | DSPLL® |
| 類型： | 時鐘和數(shù)據(jù)恢復（CDR） |
| PLL： | 是 |
| 主要目的： | SONET/SDH，ATM 應用 |
| 輸入： | 時鐘 |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 666MHz |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 20-QFN（4x4） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 628 (CN2011-ZH PDF) |
| 其它名稱： | 336-1743-5 |
Si5010
Rev. 1.4
11
4.6. PLL Performance
The PLL implementation used in the Si5010 is fully
compliant with the jitter specifications proposed for
SONET/SDH equipment by Bellcore GR-253-CORE,
Issue 3, September 2000 and ITU-T G.958.
4.6.1. Jitter Tolerance
The Si5010’s tolerance to input jitter exceeds that of the
Bellcore/ITU mask shown in Figure 4. This mask
defines the level of peak-to-peak sinusoid jitter that
must be tolerated when applied to the differential data
input of the device.
Figure 4. Jitter Tolerance Specification
4.6.2. Jitter Transfer
The Si5010 is fully compliant with the relevant Bellcore/
ITU specifications related to SONET/SDH jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a function of jitter frequency (see
Figure 5). These measurements are made with an input
test signal that is degraded with sinusoidal jitter whose
magnitude is defined by the mask in Figure 4.
4.6.3. Jitter Generation
The Si5010 meets all relevant specifications for jitter
generation proposed for SONET/SDH equipment. The
jitter generation specification defines the amount of jitter
that may be present on the recovered clock and data
outputs when a jitter free input signal is provided. The
Si5010 typically generates less than 1.6 mUIrms of jitter
when presented with jitter-free input data.
Figure 5. Jitter Transfer Specification
4.7. Powerdown
The Si5010 provides a powerdown pin, PWRDN/CAL,
that disables the device. When the PWRDN/CAL pin is
driven high, the positive and negative terminals of
CLKOUT and DOUT are each tied to VDD through
100
Ω on-chip resistors. This feature is useful in
reducing
power
consumption
in
applications
that
employ redundant serial channels. When PWRDN/CAL
is released (set to low) the digital logic resets to a
known initial condition, recalibrates the DSPLL, and
will begin to lock to the data stream.
Note: LOL is not asserted when the device is in the power-
down state.
4.8. Device Grounding
The Si5010 uses the GND pad on the bottom of the
20-pin QFN package for device ground. This pad should
be connected directly to the analog supply ground. See
4.9. Bias Generation Circuitry
The Si5010 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces
power
consumption
versus
traditional
implementations that use an internal resistor. The bias
generation circuitry requires a 10 k
Ω (1%) resistor
connected between REXT and GND.
f0
f1
f2
f3
ft
Frequency
0.15
1.5
15
Sinusoidal
Input
Jitter (U I p-p)
Slope = 20 dB /Decade
SONET
Data Rate
F0
(Hz)
F1
(Hz)
F2
(Hz)
F3
(kHz)
Ft
(kHz)
OC-12
OC-3
10
30
300
25
6.5
250
65
Fc
Frequency
Jitter
Transfer
0.1 dB
Acceptable
Range
20 dB/Decade
Slope
SONET
Data Rate
OC-12
OC-3
Fc
(kHz)
500
130
相關PDF資料 |
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| SI5013-D-GM | IC CLOCK/DATA RECOVERY 28MLP |
| SI5017-D-GM | IC CLOCK/DATA RECOVERY 28MLP |
| SI5018-B-GM | IC CLOCK/DATA RECOVERY 20-QFN |
| SI5020-B-GM | IC CLK DATA REC SONET/SDH 20-QFN |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SI5010-B-GMR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 OC-3/12 STM-1/4 Sonet/SDH CDR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5010-BM | 功能描述:計時器和支持產(chǎn)品 SONET/SDH 2.5 V OC-3/12 STM-1/4 RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| SI5010-BMR | 功能描述:計時器和支持產(chǎn)品 SONET/SDH 2.5 V OC-3/12 STM-1/4 RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| SI5010-EVB | 功能描述:時鐘和定時器開發(fā)工具 SONET/SDH 2.5 V OC-3/12 STM-1/4 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5010-GM | 制造商:SILABS 制造商全稱:SILABS 功能描述:OC-12/3, STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC |
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