參數(shù)資料
型號: SI4122-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 13/36頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR SI4122
標準包裝: 1
類型: 合成器
適用于相關產(chǎn)品: SI4122
所含物品: 板和光盤
Si4133
20
Rev. 1.61
3.10. Auxiliary Output (AUXOUT)
The signal appearing on AUXOUT is selected by setting the AUXSEL bits in the Main Configuration register
(Register 0).
The LDETB signal can be selected by setting the AUXSEL bits to 11. This signal can be used to indicate that the IF
or RF PLL is going to lose lock because of excessive ambient temperature drift and should be re-tuned. The
LDETB signal indicates a logical OR result if both IF and RF are simultaneously generating a signal.
Figure 18. Typical IF Output Voltage vs. Load Resistance at 550 MHz
Table 11. Powerdown Configuration
PWDN Pin
AUTOPDB
PDIB
PDRB
IF Circuitry RF Circuitry
PWDN = 0
XX
X
OFF
PWDN = 1
00
0
OFF
00
1
OFF
ON
01
0
ON
OFF
01
1
ON
1x
x
ON
0
50
100
150
200
250
300
350
400
450
0
200
400
600
800
1000
1200
Load Resistance ()
Output
Vol
tage
(m
Vrm
s
)
LPWR=0
LPWR=1
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