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| 型號(hào)： | SI3452MS8-KIT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 32/36頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR SI3452 |
| 特色產(chǎn)品： | Si3452 Quad High-Voltage Port Controller for PoE and PoE+PSEs |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 特殊用途 DC/DC，以太網(wǎng)供電（POE） |
| 板類(lèi)型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | Si3452 |
| 其它名稱(chēng)： | 336-1836 |
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Si3452
Rev. 1.3
5
Table 2. Recommended Operating Conditions
Description
Symbol
Test Conditions
Min
Typ
Max
Unit
Ambient Operating
Temperature
TA
–40
—
85
°C
Thermal Impedance*
θJA
No airflow
—
32
—
°C/W
1 m/s airflow
—
28
—
Power Supply Voltages
VEE Supply Voltage
VEE
For IEEE 802.3af (15.4 W) apps.
–57
–48
–45
V
For IEEE 802.3at (30 W) apps.
–57
–54
–51
VDD Supply Voltage
VDD
3.0
3.3
3.6
V
Power Supply Currents
VEE Supply Current
IEE
All ports on, excluding load current.
—
3.7
6.0
mA
All ports in shutdown mode
—
1
2
VDD Supply Current
IDD
—8
14
mA
*Note:
Modeled with six parts evenly spaced on a 30 x 120 mm2, four-layer board with 25 thermal vias to a Vneg plane on the
back.
Table 3. UVLO, and Reset Specifications
Description
Symbol
Test Conditions
Min
Typ
Max
Unit
VDD Reset Threshold
VRST
—1.75
—
V
VDD Power-On Ramp*
Ramp from 0 V to 3.0 V
—
1
ms
RST Input High Voltage
0.7 x VDD
——
V
RST Input Low Voltage
—
0.8
V
RST Input Leakage
RST =0V
—
40
μA
Reset Time Delay
TRSTDLY
Time between end of reset and
beginning of normal operation
——
100
ms
Reset Assertion Time
TRST
RST low time to generate system
reset
15
—
μs
VEE Monitor Accuracy
VEEMON
Measured VEE relative to actual
VEE for VEE (–44 to –57 V)
–4
—
4
%
VEE UVLO Threshold
VUVLO
Point at which VEE UVLO is
declared.
VEE going negative
VEE going positive
–38
—
–36
–33
—
–31
V
*Note:
If VDD ramp time is slower than 1 ms, hold the reset pins low until VDD is above 3.0 V to insure proper reset
operation.
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