參數(shù)資料
型號: SI3452D-B01-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 32/36頁
文件大?。?/td> 0K
描述: IC POE CONTROLLER MIDSPAN 40QFN
特色產(chǎn)品: Si3452 Quad High-Voltage Port Controller for PoE and PoE+PSEs
標(biāo)準(zhǔn)包裝: 50
控制器類型: 以太網(wǎng)供電控制器(POE)
接口: I²C
電源電壓: 3 V ~ 3.6 V
電流 - 電源: 14mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-QFN(6x6)
包裝: 管件
配用: SMARTPSE24-KIT-ND - KIT EVAL REF 24PORT SPI/UART
其它名稱: 336-1835-5
Si3452
Rev. 1.3
5
Table 2. Recommended Operating Conditions
Description
Symbol
Test Conditions
Min
Typ
Max
Unit
Ambient Operating
Temperature
TA
–40
85
°C
Thermal Impedance*
θJA
No airflow
32
°C/W
1 m/s airflow
28
Power Supply Voltages
VEE Supply Voltage
VEE
For IEEE 802.3af (15.4 W) apps.
–57
–48
–45
V
For IEEE 802.3at (30 W) apps.
–57
–54
–51
VDD Supply Voltage
VDD
3.0
3.3
3.6
V
Power Supply Currents
VEE Supply Current
IEE
All ports on, excluding load current.
3.7
6.0
mA
All ports in shutdown mode
1
2
VDD Supply Current
IDD
—8
14
mA
*Note:
Modeled with six parts evenly spaced on a 30 x 120 mm2, four-layer board with 25 thermal vias to a Vneg plane on the
back.
Table 3. UVLO, and Reset Specifications
Description
Symbol
Test Conditions
Min
Typ
Max
Unit
VDD Reset Threshold
VRST
—1.75
V
VDD Power-On Ramp*
Ramp from 0 V to 3.0 V
1
ms
RST Input High Voltage
0.7 x VDD
——
V
RST Input Low Voltage
0.8
V
RST Input Leakage
RST =0V
40
μA
Reset Time Delay
TRSTDLY
Time between end of reset and
beginning of normal operation
——
100
ms
Reset Assertion Time
TRST
RST low time to generate system
reset
15
μs
VEE Monitor Accuracy
VEEMON
Measured VEE relative to actual
VEE for VEE (–44 to –57 V)
–4
4
%
VEE UVLO Threshold
VUVLO
Point at which VEE UVLO is
declared.
VEE going negative
VEE going positive
–38
–36
–33
–31
V
*Note:
If VDD ramp time is slower than 1 ms, hold the reset pins low until VDD is above 3.0 V to insure proper reset
operation.
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