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參數(shù)資料
| 型號： | SI3220DC0-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 73/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | DAUGHTER CARD W/SI3200 INTERFACE |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | Si3220 |
| 已供物品： | 板，CD |
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Si3220/25 Si3200/02
Rev. 1.3
63
Not
Recommended
fo
r N
ew
D
esi
gn
s
clocks are turned back ON, the IIR filter experiences a
discontinuity in the input signal.
By writing power-down register 124 (decimal) with
0xC0, the clocks to the digital synthesis filter are forced
to be continuously ON at all times, and the TX audio
path is also kept ON so that the IIR filter continues to
run and receive continuous signal samples from the TX
channel no matter what state the SLIC is in.
Register 124 is a protected register, which must be
unlocked, then written, then locked again to prevent
unintended modification of its contents. The sequence
to write register 124 is as follows:
1. 0x2, 0x6, 0xC, 0x0 -> Reg.87 (decimal)
\\unlock protected registers
2. 0xC0 -> Reg.124 (decimal)
\\force HSP (high-speed processing) clocks to ON
3. 0x2, 0x6, 0xC, 0x0 -> Reg.87 (decimal)
\\lock protected registers
To
ensure
proper
device
operation,
the
digital
impedance synthesis coefficients (registers 33-52,
decimal) should be programmed while the LINEFEED
state is set to zero (OPEN) and register 124 is set to
0x80. After loading the digital impedance synthesis
coefficients, register 124 should be set to 0xC0. The
following sequence should always be used to program
the digital impedance synthesis coefficients:
Channel A
1. 0x2, 0x6, 0xC, 0x0
Reg. 87 (decimal) ;unlock
protected registers
2. 0x80
Reg. 124 (decimal) ;disable clock
Channel B
3. 0x80
Reg. 124 (decimal) ;disable clock
Both channels
4. Write registers 331–52 with the digital impedance
synthesis coefficients
Channel A
5. 0xC0
Reg. 124 (decimal) ;enable clock
Channel B
6. 0xC0
Reg. 124 (decimal) ;enable clock
7. 0x2, 0x6, 0xC, 0x0
Reg. 87 (decimal) ;lock
protected registers
During device initialization, steps 1, 5, 6, and 7 should
always be performed even if the digital impedance
synthesis coefficients are not programmed.
3.19. Transhybrid Balance Filter
The Dual ProSLIC devices provide a transhybrid
balance function via a digitally-programmable balance
filter block. (See “H” block in Figure 11.) The Dual
ProSLIC devices implement an 8-tap FIR filter and a
second-order IIR filter, both running at a 16 kHz sample
rate. These two filters combine to form a digital replica
of the reflected signal (echo) from the transmit path
inputs. The user can filter settings on a per-line basis by
loading the desired impedance cancellation coefficients
into the appropriate registers. The Si322x Coefficient
Generator software interface is provided for calculating
the appropriate coefficients for the FIR and IIR filter
blocks.
The transhybrid balance filters can be disabled to
implement loopback diagnostic modes. To disable the
transhybrid balance filter (zero cancellation), set the
HYBDIS bit in the DIGCON register to 1.
Note: The user must enter values into each register location
to ensure correct operation when the hybrid balance
block is enabled.
3.20. Tone Generators
Dual ProSLIC devices have two digital tone generators
that allow a wide variety of single or dual tone frequency
and amplitude combinations that spare the user the
effort of generating the required POTS signaling tones
on the PCM highway. DTMF, FSK (caller ID), call
progress, and other tones can all be generated on-chip.
The tones are sent to the receive or transmit paths.
(See Figure 11 on page 25.)
3.20.1. Tone Generator Architecture
A simplified diagram of the tone generator architecture
is shown in Figure 35. The oscillator, active/inactive
timers, interrupt block, and signal routing block are
connected for flexibility in creating audio signals.
Control and status register bits are placed in the figure
to indicate their association with the tone generator
architecture. The register set for tone generation is
summarized in Table 35.
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