參數資料
型號: SI3210PPTX-EVB
廠商: Silicon Laboratories Inc
文件頁數: 43/148頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR SI3210
標準包裝: 1
Si3210/Si3211
Rev. 1.61
137
Not
Recommended
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8.2.2. PCB Land Pattern: 38-Pin TSSOP
Figure 36 illustrates the recommended land pattern for the Si3210/11 TSSOP-38 package. Table 51 lists the values
for the dimensions shown in the illustration.
Figure 36. TSSOP-38 PCB Land Pattern Drawing
Table 51. PCB Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.80
E
Pad Row Pitch
0.50
X1
Pad Width
0.30
Y1
Pad Length
1.45
Notes:
1. All dimensions shown are in millimeters (mm) unless
otherwise noted.
2. Dimensioning and Tolerancing per ASME Y14.5M-1994.
3. This Land Pattern Design is based on IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition
(MMC). Least Material Condition (LMC) is calculated based
on a Fabirication Allowance of 0.05mm.
5. The recommended card reflow profile is per the JEDEC/IPC
J-STD-020 specification for Small Body Components.
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