參數(shù)資料
型號(hào)： SI3210PPTX-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 20/148頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR SI3210
標(biāo)準(zhǔn)包裝： 1
Si3210/Si3211
116
Rev. 1.61
Not
Recommended
fo
r N
ew
D
esi
gn
s
Reset settings = 0000_0000
Register 108. Enhancement Enable
Note: The Enhancement Enable register and associated features are available in silicon revisions C and later.
Si3210
Bit
D7
D6D5D4
D3D2
D1D0
Name
ILIMEN
FSKEN
DCSU
ZSEXT
LCVE
DCFIL
HYSTEN
Type
R/W
Si3211
Bit
D7
D6D5D4
D3D2
D1D0
Name
ILIMEN
FSKEN
ZSEXT
SWDB
LCVE
HYSTEN
Type
R/W
Bit
Name
Function
7ILIMEN
Current Limit Increase.
When enabled, this bit temporarily increases the maximum differential current limit at the
end of a ring burst to enable a faster settling time to a dc linefeed state.
0 = The value programmed in ILIM (direct Register 71) is used.
1 = The maximum differential loop current limit is temporarily increased to 41 mA.
6
FSKEN
FSK Generation Enhancement.
When enabled, this bit will increase the clocking rate of tone generator 1 to 24 kHz only
when the REL bit (direct Register 32, bit 6) is set. Also, dedicated oscillator registers are
used for FSK generation (indirect registers 99–104). Audio tones are generated using
this new higher frequency, and oscillator 1 active and inactive timers have a finer bit res-
olution of 41.67 s. This provides greater resolution during FSK caller ID signal genera-
tion.
0 = Tone generator always clocked at 8 kHz; OSC1, OSC1X., and OSC1Y are always
used.
1 = Tone generator module clocked at 24 kHz and dedicated FSK registers used only
when REL = 1; otherwise clocked at 8 kHz.
5
DCSU
DC-DC Converter Control Speedup (Si3210 only).
When enabled, this bit invokes a multi-threshold error control algorithm which allows the
dc-dc converter to adjust more quickly to voltage changes.
0 = Normal control algorithm used.
1 = Multi-threshold error control algorithm used.
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SI3211-BTR 制造商:Silicon Laboratories Inc 功能描述:
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