DOCUMENT C
參數(shù)資料
型號(hào)： SI3210-BT
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 51/148頁(yè)
文件大?。?/td> 0K
描述： IC SLIC/CODEC PROG 38TSSOP
標(biāo)準(zhǔn)包裝： 50
系列： ProSLIC®
功能： 用戶線路接口概念（SLIC），CODEC
接口： PCM，SPI
電路數(shù)： 1
電源電壓： 3.3V，5V
電流 - 電源： 88mA
功率（瓦特）： 700mW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 38-TFSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 38-TSSOP
包裝： 管件
包括： BORSCHT 功能，DTMF 生成和解碼，F(xiàn)SK 生成，脈沖測(cè)量生成，語(yǔ)音回送測(cè)試模式
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Si3210/Si3211
144
Rev. 1.61
Not
Recommended
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DOCUMENT CHANGE LIST
Revision 1.41 to Revision 1.42
16-pin ESOIC dimension A1 corrected in Table 50
Delay time between chip selects, tcs, changed from
220 ns to 440 ns in Table 10 on page 13.
C10 changed from 22 nF to 0.1 F in Figure 10 on
C18, C19 changed from 1.0 F to 4.7 F in
Recommended value for Indirect Register 40
changed from 6 to 0 in Table 44 on page 124.
Added QFN package option.
Revision 1.42 to Revision 1.43
Added TO-92 transistor suppliers to BOM.
Updated to include product revision designator.
“Lead-Free” changed to “Lead-Free and RoHS-
Compliant”
Added additional decoupling components to VDDA1,
VDDA2, and VDDD.
Added additional decoupling components to VDDA1,
VDDA2, and VDDD.
Added additional decoupling components to VDDA1,
VDDA2, and VDDD.
Added optional components to STIPE, SRINGE, and
SVBAT pins to improve idle channel noise.
Added additional decoupling components to VDDA1,
VDDA2, and VDDD.
Added optional components to STIPE, SRINGE, and
SVBAT pins to improve idle channel noise.
Changed A1 max dimension from 0.10 to 0.15.
Revision 1.43 to Revision 1.44
Updated Figure 9.
Moved the schematic for the supply filtering network for
VDDA1, VDDA2, and VDDD from the bottom of the
diagram to the top.
Moved the symbol for C26 closer to the VBATH pin on
the Si3201 symbol.
Changed R26 to 10 k
.
Added Note 5.
Updated Figure 12.
Moved the schematic for the supply filtering network for
VDDA1, VDDA2, and VDDD from the bottom of the
diagram to the top.
Moved the symbol for C9 closer to the VBATH pin on the
Si3201 symbol.
Changed R26 to 10 k
.
Added Note 4.
Updated Figure 13.
Moved the schematic for the supply filtering network for
VDDA1, VDDA2, and VDDD from the bottom of the
diagram to the top.
Added Note 5 and moved the symbol for C26 to better
illustrate its optimal position in a board layout.
Changed R26 to 10 k
.
Added Note 6.
Updated Figure 14.
Moved the schematic for the supply filtering network for
VDDA1, VDDA2, and VDDD from the bottom of the
diagram to the top.
Added Note 3 and moved the symbol for C26 to better
illustrate its optimal position in a board layout.
Added Note 4.
Changed R26 to 10 k
.
Corrected connection between D1 and the linefeed
components.
Added Note 5
Updated Table 3.
Corrected longitudinal current per pin for EBTO/
EBTA = 10 to 12 mA.
Updated Table 8.
Filled-in typical values for IVDD and IBAT for VDDD,
VDDA =3.3 V.
Updated Table 11.
Renamed "PCLK Period Jitter Tolerance" to
"PCLK-to-FSYNC Jitter Tolerance".
Added Note 2.
Updated Table 12.
Changed current rating of L2 to 150 mA.
Added new row for R26 and changed the value to
10 k
.
Added title for AN45 to description of R28 and R29.
Added column for component package type.
Added Note 1.
Updated Table 13.
Added column for component package type.
Updated Table 14.
Added column for component package type.
Updated Table 15.
Changed current rating of L2 to 150 mA.
Added new row for R26 and changed the value to
10 k
.
Rearranged the rows for R8 through R32 to be in
numerical order.
Added column for component package type.
Added Note 1.
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