
Si306x
26
Rev. 0.9
3. The CO then responds with the CID data. After
receiving the CID data, the host processor unmutes
the upstream data output and continues with normal
operation.
4. The muting of the upstream data path by the host
processor mutes the handset in a telephone
application so the user cannot hear the
acknowledgement tone and CID data being sent.
5. The CALD and RCALD bits can be cleared to re-
enable the automatic calibration when going off-
hook. The FOH[1:0] bits also can be programmed to
01 to restore the default off-hook counter time.
Because of the nature of the low-power ADC, the data
presented on SDO could have up to a 10% dc offset.
The caller ID decoder must either use a high pass or a
band pass filter to accurately retrieve the caller ID data.
6.25. Overload Detection
The Si306x can be programmed to detect an overload
condition that exceeds the normal operating power
range of the DAA circuit. To use the overload detection
feature, the following steps should be followed:
1. Set the OH bit (Register 5, bit 0) to go off-hook, and
wait 25 ms to allow line transients to settle.
2. Enable overload detection by then setting the OPE
bit (Register 17, bit 3).
If the DAA senses an overload situation, it automatically
presents an 800
impedance to the line to reduce the
hookswitch current. At this time, the DAA also sets the
OPD bit (Register 19, bit 0) to indicate that an overload
condition exists. The line current detector within the
DAA has a threshold that is dependant upon the ILIM bit
(Register 26). When ILIM = 0, the overload detection
threshold equals 160 mA. When ILIM = 1, the overload
detection threshold equals 60 mA. The OPE bit should
always be cleared before going off-hook.
6.26. Gain Control
The DAA supports different gain and attenuation
settings depending on the line-side device being used.
For all line-side devices, gains of 0, 3, 6, 9, and 12 dB
can be selected for the receive path with the ARX[2:0]
bits. The receive path can also be muted with the RXM
bit. Attenuations of 0, 3, 6, 9, and 12 dB can also be
selected for the transmit path with the ATX[2:0] bits. The
transmit path also can be muted with the TXM bit.
The signal flow through the DAA line-side and
integrated module is shown in Figures
9 and
10.6.27. Clock Generation
The Si306x line-side device connects to a system-side
module that is in turn integrated into a host processor.
The Si306x line-side receives all clocking from this
module and does not need any other clock inputs. The
sample rate for the Si306x is controlled by the Sample
Rate Control Register.
Figure 8. Implementing Type II Caller ID on the Si306x
Notes:
1.
The off-hook counter and calibrations prevent transmission or reception of data for 402.75 ms (default) for the line
voltage to settle.
2.
The caller alert signal (CAS) tone transmits from the CO to signal an incoming call.
3.
The device is taken on-hook to read the line voltage in the LVS bits to detect parallel handsets. In this mode, no data is
transmitted on the SDO pin.
4.
When the device returns off-hook, the normal off-hook counter is reduced to 8 ms. If the CALD and RCALD bits are set,
then the automatic calibrations are not performed.
5.
After allowing the off-hook counter to expire (8 ms), normal transmission and reception can continue. If CID data
reception is required, send the appropriate signal to the CO at this time.
FOH[1] Bit
RCALD Bit
CALD Bit
OH Bit
FOH[0] Bit
CA S T one
Re ce i ve d
On-Hook
O f f -Hook Counter
(8 m s )
O ff-Ho o k
A c k
LINE
On-Hook
Off-H ook C ounter
and C alibration
(402.75 ms nominally)
O ff-Ho o k
1
23
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