參數(shù)資料
型號(hào)： SI3062-F-FS
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 18/62頁(yè)
文件大?。?/td> 0K
描述： IC DAA ENH FCC LINE-SIDE 16SOIC
標(biāo)準(zhǔn)包裝： 48
功能： 直接存取裝置（DAA）
電路數(shù)： 1
電流 - 電源： 9mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC N
包裝： 管件
包括： 結(jié)帳音調(diào)檢測(cè)，線路電壓監(jiān)視器，回路電流監(jiān)視器，過(guò)載檢測(cè)，振鈴檢測(cè)器
Si306x
Rev. 0.9
25
mode is typically used to detect caller ID data and is
enabled by setting the ONHM bit (Register 5, bit 3).
Caller ID data can be gained up or attenuated using the
receive gain control bits in Register 15.
6.24. Caller ID
With the Si306x, caller ID data can be passed from the
phone line to a caller ID decoder connected to the serial
port.
6.24.1. Type I Caller ID
Type I Caller ID sends the CID data while the phone is
on-hook.
In systems where the caller ID data is passed on the
phone line between the first and second rings, utilize the
following method to capture the caller ID data:
1. After identifying a ring signal using one of the
methods described in "6.17. Ring Detection" on
page 22, determine when the first ring is complete.
2. Assert the ONHM bit (Register 5, bit 3) to enable
caller ID data detection. The caller ID data passed
across the RNG 1/2 pins is presented to the host via
the SDO pin.
3. Clear the ONHM bit after the caller ID data is
received.
In systems where the caller ID data is preceded by a
line polarity (battery) reversal, use the following method
to capture the caller ID data:
1. Enable full wave rectified ring detection (RFWE,
Register 18, bit 1).
2. Monitor the RDTP and RDTN register bits to identify
if a polarity reversal or a ring signal has occurred. A
polarity reversal trips either the RDTP or RDTN ring
detection bits, and thus the full-wave ring detector
must be used to distinguish a polarity reversal from a
ring. The lowest specified ring frequency is 15 Hz;
therefore, if a battery reversal occurs, the DSP
should wait a minimum of 40 ms to verify that the
event observed is a battery reversal and not a ring
signal. This time is greater than half the period of the
longest ring signal. If another edge is detected
during this 40 ms pause, this event is characterized
as a ring signal and not a battery reversal.
3. Assert the ONHM bit (Register 5, bit 3) to enable
caller ID data detection. The caller ID data passed
across the RNG 1/2 pins is presented to the data to
the host via the SDO pin.
4. Clear the ONHM bit after the caller ID data is
received.
6.24.2. Type II Caller ID (Si3063 and Si3064 Line-Side
Devices Only)
Type II Caller ID sends the CID data while the phone is
off-hook and is often referred to as caller ID/call waiting
(CID/CW). To receive the CID data while off-hook, use
the following procedure (see Figure 8):
1. The Caller Alert Signal (CAS) tone is sent from the
Central Office (CO) and is digitized along with the
line data. The host processor must detect the
presence of this tone.
2. The DAA must then check for another parallel device
on the same line. This is accomplished by briefly
going on-hook, measuring the line voltage, and then
returning to an off-hook state.
a. Set the CALD bit (Register 17, bit 5) to disable
the calibration that automatically occurs when
going off-hook.
b. Set the RCALD bit (Register 25, bit 5) to disable
the resistor calibration from occurring when
going off-hook.
c. Set the FOH[1:0] bits (Register 31, bits 6:5) to 11
to reduce the off-hook counter time to 8 ms.
d. Clear the OH bit to put the DAA in an on-hook
state. The RXM bit (Register 19, bit 3) may also
be set to mute the receive path.
e. Read the LVS bits to determine the state of the
line.
If the LVS bits read the typical on-hook line
voltage, then no parallel devices are active on
the line and CID data reception can be
continued.
If the LVS bits read well below the typical on-
hook line voltage, then one or more devices are
present and active on the same line that are not
compliant with Type II CID. Do not continue CID
data reception.
f. Set the OH bit to 1 to return to an off-hook state.
After returning to an off-hook state and waiting 8
ms for the off-hook counter, normal data
transmission and reception can proceed. If a
non-compliant parallel device is present, then a
reply tone is not sent by the host tone generator
and the CO does not proceed with sending the
CID data. If all devices on the line are Type II CID
compliant, then the host must mute its upstream
data output to avoid propagation of its reply tone
and the subsequent CID data. After muting its
upstream data output, the host processor should
then return an acknowledgement (ACK) tone to
the CO to request the transmission of the CID
data.
相關(guān)PDF資料
PDF描述
VE-26N-IX-S CONVERTER MOD DC/DC 18.5V 75W
S9S08SG32E1WTLR IC MCU 8BIT 32KB FLASH 28TSSOP
VE-26L-IX-S CONVERTER MOD DC/DC 28V 75W
VE-26K-IY-B1 CONVERTER MOD DC/DC 40V 50W
MCHC908QY4CDWE IC MCU 4K FLASH W/ADC 16-SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SI3062-F-FSR 制造商:Silicon Laboratories Inc 功能描述:INTEGRATED DIRECT ACCESS ARRANGEMENT 16SOIC - Tape and Reel
SI3062-X-FS 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GLOBAL LINE-SIDE DAA FOR EMBEDDED SYSTEM-SIDE MODULE
SI3063 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GLOBAL LINE-SIDE DAA FOR EMBEDDED SYSTEM-SIDE MODULE
Si3063-F-FS 功能描述:電信線路管理 IC Enhanced V.92 Global Line-Side RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
SI3063-F-FSR 制造商:Silicon Laboratories Inc 功能描述:INTEGRATED DIRECT ACCESS ARRANGEMENT 16SOIC - Tape and Reel
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*