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參數(shù)資料
| 型號： | SI3056-D-FS |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 81/94頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYSTEM-SIDE DAA 16SOIC |
| 標準包裝： | 48 |
| 數(shù)據格式： | V.92 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC N |
| 包裝： | 管件 |
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Si3056
Si3018/19/10
82
Rev. 1.05
Reset settings = 0000_0000
Register 59. Spark Quenching Control
Bit
D7D6D5D4
D3
D2D1D0
Name
TB3
SQ1
SQ0
RG1
GCE
Type
R/W
Bit
Name
Function
7
TB3
For South Korea PTT compliance, set this bit, in addition to the RZ bit, to synthesize a ringer
impedance to meet South Korea ringer impedance requirements. This bit should only be set
to meet South Korea PTT requirements and should only be set in conjunction with the RZ bit.
6SQ1
Spark Quenching.
This bit, in combination with the OHS bit (Register 16), and the OHS2 bit (Register 31), sets
the amount of time for the line-side device to go on-hook. The on-hook speeds specified are
measured from the time the OH bit is cleared until loop current equals zero.
OHS
OHS2
SQ[1:0]
Mean On-Hook Speed
0
00
Less than 0.5 ms
0
1
00
3 ms ±10% (meets ETSI standard)
1
X
11
26 ms ±10% (meets Australia spark quenching
spec)
5
Reserved Always write this bit to zero.
4SQ0
Spark Quenching.
This bit, in combination with the OHS bit (Register 16), and the OHS2 bit (Register 31), sets
the amount of time for the line-side device to go on-hook. The on-hook speeds specified are
measured from the time the OH bit is cleared until loop current equals zero.
OHS
OHS2
SQ[1:0]
Mean On-Hook Speed
0
00
Less than 0.5 ms
0
1
00
3 ms ±10% (meets ETSI standard)
1
X
11
26 ms ±10% (meets Australia spark quenching
spec)
3
Reserved Always write this bit to zero.
2RG1
Receive Gain 1 (Line-side Revision E or later).
This bit enables receive path gain adjustment.
0 = No gain applied to hybrid, full scale RX on line = 0 dBm.
1 = 1 dB of gain applied to hybrid, full scale RX on line = –1 dBm.
1GCE
Guarded Clear Enable (Line-side Revision E or later).
This bit (in conjunction with the RZ bit set to 1), enables the Si3056 to meet BT’s Guarded
Clear Spec (B5 6450, Part 1: 1993, Section 15.4.3.3). With these bits set, the DAA will draw
approximately 2.5 mA of current from the line while on-hook.
0 = default, DAA does not draw loop current.
1 = Guarded Clear enabled, DAA draws 2.5 mA while on-hook to meet Guarded Clear
requirement.
0
Reserved Always write this bit to zero.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SI3056-D-FSR | 功能描述:電信線路管理 IC Si3056 DAA System Side SSI Interface RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI3056-D-ZS3R | 制造商:Silicon Laboratories Inc 功能描述:MODEM CHIP CHIPSET 56KBPS - Tape and Reel |
| SI3056-F-FS | 制造商:Silicon Laboratories Inc 功能描述: |
| SI3056-FS | 功能描述:IC SYSTEM-SIDE DAA 16SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 調制解調器 - IC 和模塊 系列:- 標準包裝:25 系列:- 數(shù)據格式:V.21，V.22，V.23，V.29，V.32，V.34，V.90，V.92，Bell 103，Bell 212A 波特率:33.6k 電源電壓:3.3V 安裝類型:- 封裝/外殼:- 供應商設備封裝:- 包裝:托盤 配用:591-1013-ND - KIT DEV SOCKETMODEM PARALLEL591-1009-ND - KIT DEV SRL SOCKETMODEM UNIVERSL 其它名稱:MT5656SMI-P-V-34.R2-SPMT5656SMI-P-V-34.R2-SP-NDQ4711574 |
| SI3056-FSR | 制造商:Silicon Laboratories Inc 功能描述:SI3056 DAA SYSTEM-SIDE, SSI INTERFACE - LEAD-FREE SOIC 0 TO - Tape and Reel |
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