參數(shù)資料
型號: SI2400URT-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 21/94頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR SI2400 ISOMODEM
標(biāo)準(zhǔn)包裝: 1
系列: ISOmodem®
主要目的: 電信,調(diào)制解調(diào)器
嵌入式:
已用 IC / 零件: SI2400
主要屬性: 雙路 RJ-11 連接至電話線路,音頻連接器
次要屬性: RS-232,TTL 串行和 USB 接口
已供物品: 板,調(diào)制解調(diào)器,電源
相關(guān)產(chǎn)品: SI2400-BS-ND - IC ISOMODEM SYSTEM-SIDE 16SOIC
SI2400-FS-ND - IC ISOMODEM SYST-SIDE DAA 16SOIC
336-1093-ND - IC ISOMODEM SYSTEM-SIDE 16SOIC
其它名稱: 336-1166
Si2400
28
Rev. 1.3
5.16. Clock Generation Subsystem
The Si2400 contains an on-chip clock generator. Using
a single master clock input, the Si2400 can generate all
modem sample rates necessary to support V.22bis,
V.22/Bell212A, and V.21/Bell103 standards and a
9.6 kHz rate for audio playback. Either a 4.9152 MHz
clock on XTALI or a 4.9152 MHz crystal across XTALI
and XTALO form the master clock for the Si2400. This
clock source is sent to an internal phase-locked loop
(PLL) which generates all necessary internal system
clocks. The PLL has a settling time of ~1 ms. Data on
RXD should not be sent to the device prior to settling of
the PLL.
The CLKOUT pin outputs a 78.6432 MHz/(N + 1) clock
which may be used to clock a microcontroller or other
devices in the system. N may be programmed via
SE1[4:0] (CLKD) to any value from 1 to 31. N defaults to
7 on power-up. CLKOUT is disabled by setting N = 0.
SE1[7:6] (MCKR)
allows
the
user
to
control
the
microcontroller clock rate. On powerup, the Si2400
UART DTE rate is set to 2400 bps, given that the clock
input is 4.9152 MHz. The MCKR register conserves
power via slower clocking of the microcontroller for
specific applications where power conservation is
required. Table 16 shows the configurations for different
values of MCKR.
Table 15. Handshaking Control Registers
Register
Name
Function
Units
Default
S1E
TATL
Transmit Answer Tone Length
1 sec
0x03
S1F
ATTD
Answer Tone to Transmit Delay
5/3 msec
0x2D
S20
UNL
Unscrambled Ones Length—V.22
5/3 msec
0x5D
S21
TSOD
Transmit Scrambled Ones Delay—V.22
53.3 msec
0x09
S22
TSOL
Transmit Scrambled Ones Length—V.22
5/3 msec
0xA2
S23
VDDL
V.22/22b Data Delay Low
5/3 msec
0xCB
S24
VDDH
V.22/22b Data Delay High
(256) 5/3 msec
0x08
S25
SPTL
S1 Pattern Time Length V.22b
5/3 msec
0x3C
S26
VTSO
V.22b 1200 bps Scrambled Ones Length
53.3 msec
0x0C
S27
VTSOL
V.22b 2400 bps Scrambled Ones Length Low
5/3 msec
0x78
S28
VTSOH
V.22b 2400 bps Scrambled Ones Length High
(256) 5/3 msec
0x08
S2A
RSO
Receive Scrambled Ones V.22b Length
5/3 msec
0xD2
S2F
FCD
FSK Connection Delay Low
5/3 msec
0x3C
S30
FCDH
FSK Connection Delay High
(256) 5/3 msec
0x00
S31
RATL
Receive Answer Tone Length
5/3 msec
0x3C
S34
TASL
Answer Tone Length (only used in S1E [TATL] = 0x00)
5/3 msec
0x5A
S35
RSOL
Receive V.22 Scrambled Ones Length
5/3 msec
0xA2
Table 16. MCKR Configurations
SE1[7:6]
(MCKR)
Controller
Clock (MHz)
Modes
0 0
9.8304 MHz
All (default)
0 1
4.9152 MHz
All except V.22bis,
PCM
1 0
2.4576 MHz
Command only
1 1
Reserved
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