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Rev. 3.0, 04/02, page v of xxxviii
Contents
Section 1
1.1
1.2
1.3
1.4
Overview
......................................................................................................
SH7751 Series Features................................................................................................
Block Diagram.............................................................................................................
Pin Arrangement..........................................................................................................
Pin Functions...............................................................................................................
1.4.1
Pin Functions (256-Pin QFP)...........................................................................
1.4.2
Pin Functions (256-Pin BGA)..........................................................................
1
1
10
11
13
13
24
Section 2
2.1
2.2
Programming Model
..................................................................................
Data Formats ...............................................................................................................
Register Configuration.................................................................................................
2.2.1
Privileged Mode and Banks.............................................................................
2.2.2
General Registers ............................................................................................
2.2.3
Floating-Point Registers...................................................................................
2.2.4
Control Registers.............................................................................................
2.2.5
System Registers.............................................................................................
Memory-Mapped Registers..........................................................................................
Data Format in Registers..............................................................................................
Data Formats in Memory..............................................................................................
Processor States...........................................................................................................
Processor Modes..........................................................................................................
35
35
36
36
39
41
43
44
46
47
47
48
49
2.3
2.4
2.5
2.6
2.7
Section 3
3.1
Memory Management Unit (MMU)
......................................................
Overview.....................................................................................................................
3.1.1
Features...........................................................................................................
3.1.2
Role of the MMU............................................................................................
3.1.3
Register Configuration.....................................................................................
3.1.4
Caution ...........................................................................................................
Register Descriptions...................................................................................................
Address Space..............................................................................................................
3.3.1
Physical Address Space...................................................................................
3.3.2
External Memory Space...................................................................................
3.3.3
Virtual Address Space .....................................................................................
3.3.4
On-Chip RAM Space.......................................................................................
3.3.5
Address Translation.........................................................................................
3.3.6
Single Virtual Memory Mode and Multiple Virtual Memory Mode ..................
3.3.7
Address Space Identifier (ASID)......................................................................
TLB Functions.............................................................................................................
3.4.1
Unified TLB (UTLB) Configuration................................................................
51
51
51
51
54
54
55
58
58
61
62
63
63
64
64
65
65
3.2
3.3
3.4