參數(shù)資料
型號(hào)： SG6901ASZ
廠商： Fairchild Semiconductor
文件頁(yè)數(shù)： 16/19頁(yè)
文件大?。?/td> 714K
描述： IC PFC CTLR AVERAGE CURR 20SOIC
標(biāo)準(zhǔn)包裝： 1
模式： 平均電流
頻率 - 開關(guān)： 65kHz
電流 - 啟動(dòng)： 10µA
電源電壓： 12 V ~ 20 V
工作溫度： -30°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SOIC
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： SG6901ASZDKR
 
?2008 Fairchild Semiconductor Corporation
 
www.fairchildsemi.com
SG6901A " Rev. 1.0.2
16
To achieve good power factor, the voltage for V
RMS
 and
V
EA
 should be kept as constant as possible, according
to Equation 5. Good RC filtering for V
RMS
 and narrow
bandwidth (lower than the line frequency) for voltage
loop are suggested for better input current shaping.
The   transconductance   error   amplifier   has   output
impedance ZO and a capacitor C
EA
  (1礔 ~ 10礔)
should be connected to ground. This establishes a
dominant pole f1 for the voltage loop:
EA
O
1
C
Z
2
1
 
 
f
?/DIV>
?/DIV>
=
?/DIV>
 
(5)
 
The average total input power can be expressed as:
AC
EA
2
RMS
EA
AC
RMS
2
RMS
EA
AC
RMS
MO
RMS
(rms)
IN
(rms)
IN
R
V
2
V
V
R
Vin
V
V
V
I
V
I
V
I
V
Pin
?/DIV>
=
?/DIV>
?/DIV>

?/DIV>
?/DIV>

?/DIV>

?/DIV>
=
 
(6)
From Equation 6, V
EA
, the output of the voltage error
amplifier, controls the total input power and the power
delivered to the load. 
Figure 26. Average-Current-Mode Control Loop
Multi-Vector Error Amplifier
Although the PFC stage has a low bandwidth voltage
loop for better input power factor, the innovative multi-
vector error amplifier provides a fast transient response
to clamp the overshoot and undershoot of the PFC
output voltage.
0 shows the block diagram of the multi-vector error
amplifier. When the variation of the feedback voltage
exceeds    ?%    of    the    reference    voltage,    the
transconductance   error   amplifier   adjusts its output
impedance to increase the loop response.
 
Figure 27. Multi-Vector Error Amplifier
PFC Over-Voltage Protection
Using a voltage divider from the output of PFC to the
OVP   pin,   the   PFC   output   voltage   can be safely
protected. Once the voltage on the OVP pin is over
OVPPFC, the OPFC is disabled. THE OPFC is not
enabled   again   until   the   OVP   voltage   falls   below
OVPPFC.
Cycle-by-Cycle Current Limiting
SG6901A provides cycle-by-cycle current limiting for
both PFC and PWM stages. Figure 28 shows the peak
current limit for the PFC stage. The PFC gate drive is
terminated once the voltage on the ISENSE pin goes
below V
PK
.
The voltage of V
RMS
 determines the voltage of V
PK
. The
relationship between V
PK
 and V
RMS
 is shown in Figure 28.
The amplitude of the constant current, I
p
, is determined
by the internal current reference according to:
I
P
R
1.2V
2
 
 
I
?/DIV>
=
 
(8)
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