參數(shù)資料
型號: SG2524N
廠商: 意法半導(dǎo)體
英文描述: REGULATING PULSE WIDTH MODULATORS
中文描述: 調(diào)控脈寬調(diào)制器
文件頁數(shù): 4/6頁
文件大?。?/td> 82K
代理商: SG2524N
SG1524/SG2524/SG3524
4/90 Rev 1.1 2/94
Copyright
1994
L
IN
F
IN
ITY
Microelectronics Inc.
11861 Western Avenue
Garden Grove, CA 92841
(714) 898-8121
FAX: (714) 893-2570
4
FIGURE 1 - OUTPUT STAGE DEADTIME VS. C
T
FIGURE 2 - OSCILLATOR FREQUENCY VS. R
T
AND C
T
APPLICATION NOTES
OSCILLATOR
The oscillator in the SG1524 uses an external resistor R
to
establish a constant charging current into an external capacitor
C
. While this uses more current than a series-connected RC, it
provides a linear ramp voltage at C
which is used as a time-
dependent reference for the PWM comparator. The charging
current is equal to 3.6V/R
, and should be restricted to between
30
μ
A and 2mA. The equivalent range for R
T
is 1.8K to 100K.
The range of values for C
also has limits, as the discharge time
of C
determines the pulse width of the oscillator output pulse.
The pulse is used (among other things) as a blanking pulse to
both outputs to insure that there is no possibility of having both
outputs on simultaneously during transitions. This output
deadtime relationship is shown in Figure 1. A pulse width below
0.35 microseconds may cause failure of the internal flip-flop to
toggle. This restricts the minimum value of C
to 1000pF. (Note:
Although the oscillator output is a convenient oscilloscope sync
input, the probe capacitance will increase the pulse width and
decrease the oscillator frequency slightly.) Obviously, the upper
limit to the pulse width is determined by the modulation range
required in the power supply at the chosen switching frequency.
Practical values of C
fall between 1000pF and 0.1
μ
F, although
successful 120 Hz oscillators have been implemented with val-
ues up to 5
μ
F and a series surge limit resistor of 100 ohms.
The oscillator frequency is approximately 1/R
C
; where R is in
ohms, C is in microfarads, and the frequency is in Megahertz. For
greater accuracy, the chart in Figure 2 may be used for a wide
range of operating frequencies.
Note that for buck regulator topologies, the two outputs can be
wire-ORed for an effective 0-90% duty cycle range. With this
connection, the output frequency is the same as the oscillator
frequency. For push-pull applications, the outputs are used
separately; the flip-flop limits the duty cycle range at each output
to 0-45%, and the effective switching frequency at the trans-
former is 1/2 the oscillator frequency.
If it is desired to synchronize the SG1524 to an external clock, a
positive pulse may be applied to the clock pin. The oscillator
should be programmed with R
and C
values that cause it to free-
run at 90% of the external sync frequency. A sync pulse with a
maximum logic 0 of +0.3 volts and a minimum logic 1 of +2.4 volts
applied to Pin 3 will lock the oscillator to the external source. The
minimum sync pulsewidth should be 200 nanoseconds, and the
maximum is determined by the required deadtime. The clock pin
should never be driven more negative than -0.3 volts, nor more
positive than +5.0 volts. The nominal resistance to ground is
3.2K at the clock pin, ±25% over temperature.
If two or more SG1524s must be synchronized together, program
one master unit with R
and C
for the desired frequency. Leave
the R
pins on the slaves open, connect the C
pins to the C
of
the master, and connect the clock pins to the clock pin of the
master. Since C
is a high-impedance node, this sync technique
works best when all devices are close together.
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