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S-MOS Systems, Inc. 2460 North First Street San Jose, CA 95131 Tel: (408) 922-0200 Fax: (408) 922-0238
268-0.4
53
Notes:
1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15,
VRD, VWR and VCE are TTL-level inputs.
2. SEL1 and NT/PL are CMOS-level inputs. YD, XD0 to
XD3, XSCL, XECL, LP, WF, YSCL, YDIS and CLO are
CMOS-level outputs.
3. RES is a Schmitt-trigger input. The pulsewidth on RES
must be at least 200
μ
s. Note that pulses of more than
a few seconds will cause DC voltages to be applied to
the LCD panel.
4. f
OSC
= 10 MHz, no load (no display memory), internal
character generator, 256
×
200 pixel display. The
operating supply current can be reduced by approxi-
mately 1 mA by setting both CLO and the display OFF.
4.3 SED1335/1336 Electrical Characteristics
Parameter
Symbol
Condition
Rating
typ
5.0
—
0.05
0.10
11
Unit
min
4.5
2.0
—
—
—
max
5.5
6.0
2.0
5.0
15
Supply voltage
Register data retention voltage
Input leakage current
Output leakage current
Operating supply current
V
DD
V
OH
I
LI
I
LO
I
opr
V
V
μ
A
μ
A
mA
V
I
= V
DD
. See note 6.
V
I
= V
SS
. See note 6.
See note 4.
Sleep mode,
V
OSC1
= V
CS
= V
RD
= V
DD
Quiescent supply current
I
Q
—
0.05
20.0
μ
A
Oscillator frequency
External clock frequency
Oscillator feedback resistance
TTL
HIGH-level input voltage
LOW-level input voltage
f
OSC
f
CL
R
f
1.0
1.0
0.5
—
—
1.0
10.0
10.0
3.0
MHz
MHz
M
V
IHT
V
ILT
See note 1.
See note 1.
I
OH
= –5.0 mA.
See note 1.
I
OL
= 5.0 mA. See note 1.
0.5V
DD
V
SS
—
—
V
DD
0.2V
DD
V
V
HIGH-level output voltage
V
OHT
2.4
—
—
V
LOW-level output voltage
CMOS
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
Open-drain
LOW-level output voltage
Schmitt-trigger
Rising-edge threshold voltage
Falling-edge threshold voltage
V
OLT
—
—
V
SS
+ 0.4
V
V
IHC
V
ILC
V
OHC
V
OLC
See note 2.
See note 2.
I
OH
= –2.0 mA. See note 2.
V
DD
– 0.4
I
OH
= 1.6 mA. See note 2.
0.8V
DD
V
SS
—
—
—
—
V
DD
0.2V
DD
—
V
SS
+ 0.4
V
V
V
V
—
V
OLN
I
OL
= 6.0 mA. See note 5.
—
—
V
SS
+ 0.4
V
V
T+
V
T–
See note 3.
See note 3.
0.5V
DD
0.2V
DD
0.7V
DD
0.3V
DD
0.8V
DD
0.5V
DD
V
V
V
DD
= 4.5 to 5.5V, V
SS
= 0V, T
a
= –20 to 75
°
C
Measured at crystal,
47.5% duty cycle.
See note 7.
4.3
4.0 Specifications