參數(shù)資料
型號(hào): SE98ATP,547
廠商: NXP Semiconductors
文件頁數(shù): 19/43頁
文件大?。?/td> 849K
描述: IC TEMP SENSOR DDR 8-HWSON
產(chǎn)品培訓(xùn)模塊: I²C Bus Fundamentals
標(biāo)準(zhǔn)包裝: 1
功能: 溫度監(jiān)控系統(tǒng)(傳感器)
傳感器類型: 內(nèi)部
感應(yīng)溫度: -40°C ~ 125°C
精確度: ±4°C(最小值)
拓?fù)洌?/td> ADC(三角積分型),寄存器庫
輸出類型: I²C?/SMBus?
輸出警報(bào):
輸出風(fēng)扇:
電源電壓: 1.7 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 8-WSON
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 847 (CN2011-ZH PDF)
其它名稱: 568-4731-6
SE98A_4
?NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04  25 November 2009
19 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
7
CTLB
Critical Trip Lock bit.
0  Critical Alarm Trip register is not locked and can be altered (default).
1  Critical Alarm Trip register settings cannot be altered.
This bit is initially cleared. When set, this bit will return a 1, and remains locked
until cleared by internal Power-on reset. This bit can be written with a single
write and do not require double writes.
6
AWLB
Alarm Window Lock bit.
0  Upper and Lower Alarm Trip registers are not locked and can be
altered (default).
1  Upper and Lower Alarm Trip registers setting cannot be altered.
This bit is initially cleared. When set, this bit will return a 1 and remains locked
until cleared by internal power-on reset. This bit can be written with a single
write and does not require double writes.
5
CEVNT
Clear EVENT
 (write only).
0  No effect (default).
1  Clears active EVENT
 in Interrupt mode. Writing to this register has no
effect in Comparator mode.
When read, this register always returns zero.
4
ESTAT
EVENT
 Status (read only).
0  EVENT
 output condition is not being asserted by this device (default).
1  EVENT
 output pin is being asserted by this device due to Alarm
Window or Critical Trip condition.
The actual event causing the EVENT
 can be determined from the Read
Temperature register. Interrupt Events can be cleared by writing to the
Clear EVENT
 bit (CEVNT). Writing to this bit will have no effect.
3
EOCTL
EVENT
 Output Control.
0  EVENT
 output disabled (default).
1  EVENT
 output enabled.
When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot
be altered until unlocked.
2
CVO
Critical Event Only.
0  EVENT
 output on Alarm or Critical temperature event (default)
1  EVENT
 only if temperature is above the value in the critical
temperature register
When the Critical Trip or Alarm Window lock bit is set, this bit cannot be
altered until unlocked.
" Advisory note:
   JEDEC specification requires only the Alarm Window lock bit to be set.
   Work-around: Clear both Critical Trip and Alarm Window lock bits.
   Future 1.7 V to 3.6 V SE98B will require only the Alarm Window lock 
bit to be set.
Table 9.
Configuration register (address 01h) bit description &continued
Bit
Symbol
Description
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