參數(shù)資料
型號: SE98ATP,547
廠商: NXP Semiconductors
文件頁數(shù): 12/43頁
文件大?。?/td> 849K
描述: IC TEMP SENSOR DDR 8-HWSON
產(chǎn)品培訓(xùn)模塊: I²C Bus Fundamentals
標(biāo)準(zhǔn)包裝: 1
功能: 溫度監(jiān)控系統(tǒng)(傳感器)
傳感器類型: 內(nèi)部
感應(yīng)溫度: -40°C ~ 125°C
精確度: ±4°C(最小值)
拓?fù)洌?/td> ADC(三角積分型),寄存器庫
輸出類型: I²C?/SMBus?
輸出警報:
輸出風(fēng)扇:
電源電壓: 1.7 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 8-WSON
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 847 (CN2011-ZH PDF)
其它名稱: 568-4731-6
SE98A_4
?NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04  25 November 2009
12 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
7.7  SMBus Time-out
The SE98A supports the SMBus time-out feature. If the host holds SCL LOW between
25 ms and 35 ms, the SE98A would reset its internal state machine to the bus idle state to
prevent the system bus hang-up. This feature is turned on by default. The SMBus time-out
is disabled by writing a logic 1 to bit 7 of register 22h.
Remark: When SMBus time-out is enabled, the I
2
C-bus minimum bus speed is limited by
the SMBus time-out timer, and goes down to only 10 kHz.
The SE98A has no SCL driver, so it cannot hold the SCL line LOW.
Remark: SMBus time-out works over the entire supply range of 1.7 V to 3.6 V unless 
shutdown bit (SHMD) is set and turns off the oscillator.
7.8  SMBus ALERT
The SE98A supports SMBus ALERT when it is programmed for the Interrupt mode and
when the EVENT
 polarity bit is set to logic 0. The EVENT
 pin can be ANDed with other
EVENT
 or ALERT
 signals from other slave devices to signal their intention to
communicate with the host controller. When the host detects EVENT
 or ALERT
 signal
LOW, it issues an Alert Response Address (ARA) to which a slave device would respond
with its address. When there are multiple slave devices generating an ALERT the SE98A
performs bus arbitration. If it wins the bus, it responds to the ARA and then clears the
EVENT
 pin.
Remark: Either in comparator mode or when the SE98A crosses the critical temperature, 
the host must also read the EVENT
 status bit and provide remedy to the situation by
bringing the temperature to within the alarm window or below the critical temperature if
that bit is set. Otherwise, the EVENT
 pin will not get de-asserted.
Remark: In the SE98A, the ARA is set to default ON. However, in the SE98B the ARA will 
be set to default OFF since ARA is not anticipated to be used in DDR3 DIMM applications.
 
Fig 7.    How SE98A responds to SMBus ALERT
0
0
0
1
1
A2
Alert Response Address
1
1
0
0
S
0
0
0
START bit
read
acknowledge
002aab330
A1
A0
0
1
P
device address
not acknowledge
STOP bit
host NACK and
sends a STOP bit
Slave acknowledges and
sends its slave address.
The last bit of slave address
is hard coded '0'.
master sends a START bit,
ARA and a read command
host detects
SMBus ALERT
1
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