參數(shù)資料
型號(hào)： SDA9380-B21
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
元件分類： 消費(fèi)家電
英文描述： EDDC Enhanced Deflection Controller and RGB Processor
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： PLASTIC, MQFP-64
文件頁(yè)數(shù)： 2/72頁(yè)
文件大小： 366K
代理商： SDA9380-B21
SDA 9380 - B21
Preliminary Data Sheet
Micronas
i
2001-01-29
Document Change Note
DS
1
Date
Page
Changes compared to previous issue
2
3
31.03.98
17.07.98
23.07.98
23.07.98
27.07.98
07.08.98
09.09.98
14.09.98
16.09.98
16.09.98
16.09.98
16.09.98
Version 02
Document state 03 corresponds to silicon version A11
block diagram changed
bandwidth of YUV increased (new value 30 MHz)
Vertical component of SCP changed (not equals internal signal VBL!)
Pin configuration changed
Description of PMW byte changed
SCP output level changed (supply voltage for SCP is V
DD(MC)
Sequence of I2C control items changed, new
items added
Bit SLBLKS added to RGB control byte 1
Detailed description of the I2C item PWM control byte
Detailed description of the items Average beam current limit character-
istics, Peak drive limit, Soft clipping
Explanation of the items Peak dark detection top border, bottom border,
left border, right border
I2C bit KILLZIP deleted, KILLZIP function remains implemented
I2C bit HSWID deleted
I2C bit HSWMI added
Positive and negative polarity of HSYNC allowed (int. normalization)
20.10.98 1, 3, 10, 39 18.75 kHz line frequency added
27.10.98
14, 31, 32
End of V-blanking also programmable by VBE if JMP=0
12.11.98
31
Specification of end of V-blanking component of SCP changed
19.11.98
21
3 MSBs of PLL control byte 1 must be 0 instead of don’t care
24.11.98
4
Pin configuration changed
02.12.98
40
HSAFE input voltage at 31.25 kHz and 38 kHz specified
04.12.98
40
VREFP, VREFH, VREFL are internal reference voltages
04.12.98
39
Input BSOIN, delay t
D2
changed from 30 lines to 42 lines
04.12.98
15
Default value of saturation control changed form 0 to -12
18.01.99
19
I2C bus bits NR, NL2...NL0 of Vertical sync byte control deleted
21.01.99
1, 7, 11
Text changed because the vertical noise reduction has been removed
21.01.99
11
Remark for switching to external clock mode added
22.01.99
5, 6
Pin description changed
05.02.99
7, 8
Description of Black Switch Off (BSO) changed
26.02.99
37
VSS, SUBST total voltage differentials added
15.03.99
2, 14, 46
Higher resolution of D/A output (6 bit -> 8 bit), INL changed (1 -> 2 LSB)
15.03.99
15, 43
Contrast setting with resolution of 8 bit instead of 6 bit
15.03.99
15, 44
Brightness setting with resolution of 8 bit instead of 6 bit
16.03.99
43
NTSC/US matrix changed
3
46
27
4, 5, 6
14, 17, 20
43
14,15
24
20
25, 26
16.09.98
34
18.09.98
18.09.98
18.09.98
18.09.98
21
10, 21, 39
10, 21, 39
10, 39
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