- 您現(xiàn)在的位置：買賣IC網 > PDF目錄374749 > SDA9220-5 (SIEMENS A G) Memory Sync Controller III PDF資料下載
參數資料
| 型號： | SDA9220-5 |
| 廠商： | SIEMENS A G |
| 元件分類： | 消費家電 |
| 英文描述： | Memory Sync Controller III |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC44 |
| 文件頁數： | 2/42頁 |
| 文件大?。?/td> | 1474K |
| 代理商： | SDA9220-5 |
第1頁當前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
SDA 9220-5
Semiconductor Group
118
Circuit Description
The MSC III can be divided into the following function blocks (
figure 6
):
– Sync-signal generator
– Memory controller
– Clock generator
–
I
2
C Bus receiver
The sync-signal generator uses signals VS and BLN to produce the horizontal and vertical sync
signals BLN2, HS2, VS1 and VS2. It supplies the composite sync signal CSY for the 100-Hz
teletext, the control signal MUX for implementing a simple frame Featurebox and the frame signal
FRM for inserting a colored frame in multi-picture, still-in-picture and picture-in-still modes. Signal
CFH is output to prevent the bottom flutter effect in the video cassette recorder mode.
In operation without standard conversion (pin-programmable) signals BLN2, VS2 and FRM are
switched from double to single line/field frequency. Outputs CSY and HS2 are not required in this
case.
The memory controller produces the driving signals (RA, RB, WT, RE) and the addresses (SAR,
SAC) for the memory devices (TV-SAMs). In addition, it produces the DREQ pulses used for
requesting data from the picture processor during operation with reduced pictures. Two refresh
operations are performed in the memory for each TV line.
The clock generator consists essentially of a PLL which generates the internal and exported system
clocks from input clock LL3 or LL1.5 and synchronizes them with the horizontal blanking signal. The
MSC can be set to one of the two input frequencies via input LLSEL. For the possible use of the
Featurebox as a channel scanner, the PLL incorporates a crystal-controlled reference clock to
ensure an undisturbed clock supply for memory output (stills sequence) during channel-switching
phases.
All modes (except switching off the standard conversion) are set by appropriate programming of the
I
2
C Bus data bytes. When the operating voltage is switched on, all bits of the associated control
registers are set to 0. The address of the
I
2
C Bus is set with signal ADR (24
H
or 26
H
).
相關PDF資料 |
PDF描述 |
|---|---|
| SDA9251-2X | 868352-Bit Dynamic Sequential Access Memory for Television Applications (TV-SAM) |
| SDA9253 | 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) |
| SDA9254-2 | 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter |
| SDA9257 | Clock Sync Generator |
| SDA9280 | ICs for Consumer Electronics |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SDA9251-2X | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:868352-Bit Dynamic Sequential Access Memory for Television Applications (TV-SAM) |
| SDA9253 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) |
| SDA9254-2 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter |
| SDA9255 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:SRC-Scan Rate Converter SDA9255 |
| SDA9257 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Clock Sync Generator |
發(fā)布緊急采購，3分鐘左右您將得到回復。