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參數(shù)資料
| 型號： | SDA9205-2 |
| 廠商： | SIEMENS A G |
| 元件分類： | ADC |
| 英文描述： | Triple 8-Bit Analog-to-Digital-Converter |
| 中文描述： | 3-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQCC68 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大小： | 567K |
| 代理商： | SDA9205-2 |
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SDA 9205-2
Semiconductor Group
11
The digital output data are synchronized by the FSY signal. The first high of FSY defines the first
output format byte and is synchronized to CLK. In case of asynchronism the first (in formats 8:1:1,
4:1:1 the first and the second) output format byte after FSY had gone high does not contain valid
data. Timing of FSY, CLK and output data is shown in
figure 4
with output format 4:1:1.
Figure 4
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