參數(shù)資料
型號(hào): SDA5251M
廠商: SIEMENS A G
元件分類: 圖文
英文描述: ICs for Consumer Electronics
中文描述: TELETEXT AND VPS/PDC DECODER, PQFP64
文件頁(yè)數(shù): 109/143頁(yè)
文件大?。?/td> 1050K
代理商: SDA5251M
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SDA 525x
Semiconductor Group
109
1998-04-08
PWM Compare Registers PWCOMP 6, 7
PWM Extension Registers PWEXT 6, 7
Note: The described operation is independent of the setting of PWCOMP6 or
PWCOMP7.
The stretch operation is interleaved between PWM-Cycles.
PWM Compare Registers
Default after reset: 00
(MSB)
Bit 7
PWCOMP 6, 7
SFR-Address FB
H
,FD
H
H
(LSB)
Bit 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 7 - Bit 0
This bits define the high time of the output. If all bits are 0, the
high time is 0 internal clocks. If all bits are 1, the high time is
255 internal clocks.
PWM Extension Registers
Default after reset: 00
(MSB)
Bit 7
Bit 6
PWEXT 6, 7
SFR-Address FA
H
,FC
H
H
(LSB)
Bit 0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 7
If this bit is set, every second PWM-Cycle is stretched by one
internal clock.
Bit 6
If this bit is set, every fourth PWM-Cycle is stretched by one
internal clock.
Bit 5
If this bit is set, every eighth PWM-Cycle is stretched by one
internal clock.
Bit 4
If this bit is set, every 16th PWM-Cycle is stretched by one
internal clock.
Bit 3
If this bit is set, every 32th PWM-Cycle is stretched by one
internal clock.
Bit 2
If this bit is set, every 64th PWM-Cycle is stretched by one
internal clock.
Bit 1, Bit 0
This bits have to be set to 0.
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